Simulation Results: entropy_src/rng_16bits

 
20/07/2026 20:41:39 DVSim: v1.49.12 sha: 54120d8 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 67.44 %
  • code
  • 80.94 %
  • assert
  • 73.92 %
  • func
  • 47.47 %
  • block
  • 93.90 %
  • line
  • 97.57 %
  • branch
  • 85.71 %
  • toggle
  • 50.91 %
  • FSM
  • 89.58 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 48.005us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 54.676us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 83.802us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 9.000s 454.097us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 5.000s 384.496us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 2.000s 9.180us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 83.802us 1 1 100.00
entropy_src_csr_aliasing 5.000s 384.496us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 48.005us 1 1 100.00
entropy_src_rng 30.000s 13324.617us 1 1 100.00
entropy_src_fw_ov 90.000s 13340.847us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 90.000s 13340.847us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 30.000s 13324.617us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 123.000s 14101.843us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 30.000s 13324.617us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 30.000s 13324.617us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 30.000s 13324.617us 1 1 100.00
entropy_src_intr 3.000s 71.842us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 30.000s 13324.617us 1 1 100.00
entropy_src_functional_alerts 5.000s 1069.829us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 322.000s 14203.095us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 3.000s 37.575us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 14.000s 810.578us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 38.712us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 17.489us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 4.000s 289.757us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 4.000s 289.757us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 54.676us 1 1 100.00
entropy_src_csr_rw 2.000s 83.802us 1 1 100.00
entropy_src_csr_aliasing 5.000s 384.496us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 117.214us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 54.676us 1 1 100.00
entropy_src_csr_rw 2.000s 83.802us 1 1 100.00
entropy_src_csr_aliasing 5.000s 384.496us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 117.214us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 3.000s 320.255us 1 1 100.00
entropy_src_tl_intg_err 3.000s 104.528us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 30.000s 13324.617us 1 1 100.00
entropy_src_cfg_regwen 2.000s 78.087us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 30.000s 13324.617us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 30.000s 13324.617us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 30.000s 13324.617us 1 1 100.00
entropy_src_fw_ov 90.000s 13340.847us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 37.575us 1 1 100.00
entropy_src_sec_cm 3.000s 320.255us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 37.575us 1 1 100.00
entropy_src_sec_cm 3.000s 320.255us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 30.000s 13324.617us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 37.575us 1 1 100.00
entropy_src_sec_cm 3.000s 320.255us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 37.575us 1 1 100.00
entropy_src_sec_cm 3.000s 320.255us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 3.000s 37.575us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 5.000s 1069.829us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 104.528us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 44.000s 13264.889us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 12.000s 5285.717us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.alert_test 1 test run
entropy_src_stress_all_with_rand_reset 77021781190533864788195840826603601739176054454496685581711534998960242940782 492
UVM_INFO @ 5285716548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_hi_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 83451574617155046670435407487487144641984797786276197360462094441138589356982 113
UVM_INFO @ 9179895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---