Simulation Results: hmac

 
20/07/2026 20:41:39 DVSim: v1.49.12 sha: 54120d8 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.29 %
  • code
  • 95.91 %
  • assert
  • 96.96 %
  • func
  • 29.99 %
  • block
  • 97.41 %
  • line
  • 98.35 %
  • branch
  • 93.52 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 12.000s 682.333us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 29.384us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 63.368us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 13.000s 1895.776us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 7.000s 3493.446us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 37.391us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 63.368us 1 1 100.00
hmac_csr_aliasing 7.000s 3493.446us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 24.000s 2590.431us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 51.000s 3112.532us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 10.000s 454.533us 1 1 100.00
hmac_test_sha384_vectors 387.000s 31143.150us 1 1 100.00
hmac_test_sha512_vectors 24.000s 770.947us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 1322.404us 1 1 100.00
hmac_test_hmac384_vectors 16.000s 2419.742us 1 1 100.00
hmac_test_hmac512_vectors 16.000s 746.487us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 22.000s 2287.949us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 35.000s 2122.920us 1 1 100.00
error 1 1 100.00
hmac_error 64.000s 6666.606us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 47.000s 1604.586us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 12.000s 682.333us 1 1 100.00
hmac_long_msg 24.000s 2590.431us 1 1 100.00
hmac_back_pressure 51.000s 3112.532us 1 1 100.00
hmac_datapath_stress 35.000s 2122.920us 1 1 100.00
hmac_burst_wr 22.000s 2287.949us 1 1 100.00
hmac_stress_all 510.000s 223778.913us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 12.000s 682.333us 1 1 100.00
hmac_long_msg 24.000s 2590.431us 1 1 100.00
hmac_back_pressure 51.000s 3112.532us 1 1 100.00
hmac_datapath_stress 35.000s 2122.920us 1 1 100.00
hmac_wipe_secret 47.000s 1604.586us 1 1 100.00
hmac_test_sha256_vectors 10.000s 454.533us 1 1 100.00
hmac_test_sha384_vectors 387.000s 31143.150us 1 1 100.00
hmac_test_sha512_vectors 24.000s 770.947us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 1322.404us 1 1 100.00
hmac_test_hmac384_vectors 16.000s 2419.742us 1 1 100.00
hmac_test_hmac512_vectors 16.000s 746.487us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 12.000s 682.333us 1 1 100.00
hmac_long_msg 24.000s 2590.431us 1 1 100.00
hmac_back_pressure 51.000s 3112.532us 1 1 100.00
hmac_datapath_stress 35.000s 2122.920us 1 1 100.00
hmac_burst_wr 22.000s 2287.949us 1 1 100.00
hmac_error 64.000s 6666.606us 1 1 100.00
hmac_wipe_secret 47.000s 1604.586us 1 1 100.00
hmac_test_sha256_vectors 10.000s 454.533us 1 1 100.00
hmac_test_sha384_vectors 387.000s 31143.150us 1 1 100.00
hmac_test_sha512_vectors 24.000s 770.947us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 1322.404us 1 1 100.00
hmac_test_hmac384_vectors 16.000s 2419.742us 1 1 100.00
hmac_test_hmac512_vectors 16.000s 746.487us 1 1 100.00
hmac_stress_all 510.000s 223778.913us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 510.000s 223778.913us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 12.168us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 40.825us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.000s 244.251us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.000s 244.251us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 29.384us 1 1 100.00
hmac_csr_rw 2.000s 63.368us 1 1 100.00
hmac_csr_aliasing 7.000s 3493.446us 1 1 100.00
hmac_same_csr_outstanding 3.000s 431.195us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 29.384us 1 1 100.00
hmac_csr_rw 2.000s 63.368us 1 1 100.00
hmac_csr_aliasing 7.000s 3493.446us 1 1 100.00
hmac_same_csr_outstanding 3.000s 431.195us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 126.553us 1 1 100.00
hmac_tl_intg_err 2.000s 157.815us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.000s 157.815us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 12.000s 682.333us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 7.000s 280.649us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 99.000s 5594.595us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.000s 41.620us 1 1 100.00