Simulation Results

Simulation Results: i2c

20/07/2026 20:41:39 DVSim: v1.49.12 sha: 54120d8 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
88.18 %

code
85.62 %

assert
97.04 %

func
81.88 %

block
95.90 %

line
95.32 %

branch
92.63 %

toggle
72.52 %

FSM
82.01 %

Validation stages

V1		100.00%
V2		85.37%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	19.000s	5129.253us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	9.000s	4142.395us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	2.000s	22.327us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	21.527us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	5.000s	1138.285us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.000s	95.748us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	2.000s	36.009us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	21.527us	1	1	100.00
	i2c_csr_aliasing	1.000s	95.748us	1	1	100.00

35/41 passed

85.37 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.000s	139.672us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	121.000s	39498.050us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	660.000s	27572.558us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	1.000s	32.428us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	2440.000s	2981.216us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	281.000s	3795.215us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.000s	414.888us	1	1	100.00
	i2c_host_fifo_fmt_empty	32.000s	460.264us	1	1	100.00
	i2c_host_fifo_reset_rx	3.000s	146.011us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	369.000s	9970.101us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	28.000s	5307.033us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	4.000s	101.951us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	4.000s	528.597us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	3600.000s	0.000us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.000s	402.758us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	4.000s	1212.590us	1	1	100.00
	i2c_target_intr_smoke	4.000s	1538.644us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	3.000s	200.365us	1	1	100.00
	i2c_target_fifo_reset_tx	1.000s	133.676us	1	1	100.00
target_fifo_full				2	3	66.67
	i2c_target_stress_wr	17.000s	13286.372us	1	1	100.00
	i2c_target_stress_rd	4.000s	1212.590us	1	1	100.00
	i2c_target_intr_stress_wr	3601.000s	0.000us	0	1	0.00
target_timeout				1	1	100.00
	i2c_target_timeout	8.000s	1269.418us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	254.000s	1118.779us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	5.000s	752.001us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	2.000s	268.891us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.000s	931.862us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	602.680us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	660.000s	27572.558us	1	1	100.00
	i2c_host_perf_precise	3.000s	71.787us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	28.000s	5307.033us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	3.000s	292.247us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	3.000s	7565.053us	1	1	100.00
	i2c_target_nack_acqfull_addr	3.000s	436.840us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	260.021us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	15.000s	2602.445us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	3.000s	3414.373us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	1.000s	16.814us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	29.070us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.000s	86.099us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.000s	86.099us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	22.327us	1	1	100.00
	i2c_csr_rw	1.000s	21.527us	1	1	100.00
	i2c_csr_aliasing	1.000s	95.748us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	59.387us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	22.327us	1	1	100.00
	i2c_csr_rw	1.000s	21.527us	1	1	100.00
	i2c_csr_aliasing	1.000s	95.748us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	59.387us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.000s	80.960us	1	1	100.00
	i2c_sec_cm	2.000s	579.054us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.000s	80.960us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	16.000s	2168.024us	1
target_error_intr				1
	i2c_target_unexp_stop	2.000s	76.884us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	6.000s	959.970us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	89130653863207509688122991914205841503025859719771328679558649233898879449823	97	UVM_INFO @ 139671670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	895950955706515552651929514245287129130284673228777285154614932141229115375	149	UVM_INFO @ 39498050033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				2 test runs
	i2c_target_intr_stress_wr	23029245499794356252495050838486910617657711297233032821603286487408116462083	None
	i2c_target_stress_all	82237841587178921702869380900015896314177299911117022018215705545956290973698	None
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	13379728875682109671335238953953519890001221783309890968139482213098092665548	120	UVM_INFO @ 2168024152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	763964948133489903312174690324947303248891524033739920393587081893363894236	95	UVM_INFO @ 959969813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	103861072532604779060819261413777886572925234063943838940457022370904063434820	93	UVM_INFO @ 528596809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	102552523863313712941783997840302743887866337781572734874814611849945042890957	87	UVM_INFO @ 76884490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:629) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead				1 test run
	i2c_host_mode_toggle	2019069686585117090462589101190187863790571073865495462997745971730455726279	96	--> EXP: --------------------------------------------------- Name Type Size Value ---------------------------------------------------