Simulation Results: kmac/unmasked

 
20/07/2026 20:41:39 DVSim: v1.49.12 sha: 54120d8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.58 %
  • code
  • 66.31 %
  • assert
  • 95.62 %
  • func
  • 73.82 %
  • line
  • 92.81 %
  • branch
  • 87.05 %
  • cond
  • 83.96 %
  • toggle
  • 27.56 %
  • FSM
  • 40.15 %
Validation stages
V1
100.00%
V2
72.41%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 55.430s 18664.687us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.020s 37.261us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.980s 96.729us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 11.940s 1546.518us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 7.380s 1120.059us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 2.200s 76.657us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.980s 96.729us 1 1 100.00
kmac_csr_aliasing 7.380s 1120.059us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.710s 70.139us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.780s 75.959us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 2868.480s 214538.403us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 182.410s 8669.599us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1398.670s 105834.256us 1 1 100.00
kmac_test_vectors_sha3_256 2094.310s 114837.303us 1 1 100.00
kmac_test_vectors_sha3_384 960.120s 121431.612us 1 1 100.00
kmac_test_vectors_sha3_512 14.410s 1307.635us 1 1 100.00
kmac_test_vectors_shake_128 174.970s 93366.126us 1 1 100.00
kmac_test_vectors_shake_256 1404.270s 146404.228us 1 1 100.00
kmac_test_vectors_kmac 2.070s 83.224us 1 1 100.00
kmac_test_vectors_kmac_xof 2.070s 123.197us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 167.660s 3675.132us 1 1 100.00
app 0 1 0.00
kmac_app 1.070s 31.991us 0 1 0.00
app_with_partial_data 0 1 0.00
kmac_app_with_partial_data 0.920s 58.274us 0 1 0.00
entropy_refresh 0 1 0.00
kmac_entropy_refresh 7.480s 5143.225us 0 1 0.00
error 0 1 0.00
kmac_error 29.170s 1305.259us 0 1 0.00
key_error 0 1 0.00
kmac_key_error 1.150s 7.030us 0 1 0.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 0.920s 3.921us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 19.570s 464.536us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 23.450s 1588.163us 1 1 100.00
entropy_ready_error 0 1 0.00
kmac_entropy_ready_error 1.330s 116.472us 0 1 0.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.560s 178.610us 1 1 100.00
stress_all 0 1 0.00
kmac_stress_all 13.120s 1327.929us 0 1 0.00
intr_test 1 1 100.00
kmac_intr_test 0.880s 27.272us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.060s 290.236us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.420s 92.894us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.420s 92.894us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.020s 37.261us 1 1 100.00
kmac_csr_rw 0.980s 96.729us 1 1 100.00
kmac_csr_aliasing 7.380s 1120.059us 1 1 100.00
kmac_same_csr_outstanding 1.850s 73.443us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.020s 37.261us 1 1 100.00
kmac_csr_rw 0.980s 96.729us 1 1 100.00
kmac_csr_aliasing 7.380s 1120.059us 1 1 100.00
kmac_same_csr_outstanding 1.850s 73.443us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 2.680s 337.382us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 2.680s 337.382us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 2.680s 337.382us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 2.680s 337.382us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.710s 523.212us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 54.420s 6280.311us 1 1 100.00
kmac_tl_intg_err 2.590s 488.054us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.590s 488.054us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.560s 178.610us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 55.430s 18664.687us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 167.660s 3675.132us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 2.680s 337.382us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 54.420s 6280.311us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 54.420s 6280.311us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 54.420s 6280.311us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 55.430s 18664.687us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.560s 178.610us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 54.420s 6280.311us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 0 1 0.00
kmac_mubi 3.000s 672.930us 0 1 0.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 55.430s 18664.687us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 1.210s 29.955us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] 7 test runs
kmac_app 450783593758223142103265303902506625744861457948658561112240155749989457302 77
UVM_INFO @ 31990860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app_with_partial_data 86613306852020455826826989537000660821779825785639555070145146108454385798055 77
UVM_INFO @ 58274191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_refresh 39937420545795968418304082023475916525226548483481118899145631044730521794688 81
UVM_INFO @ 5143224863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_error 24375326145415321371291695674838152063897559904726510570946803173516489571093 98
UVM_INFO @ 1305259451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_ready_error 35522546530894125861511537164541178350280894518482756212102653266418168238475 77
UVM_INFO @ 116471780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 109864495202557481643871291067107790173407592740041971636500496464836505283717 92
UVM_INFO @ 1327928898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 76519385103925853138402547600247657175716489138030688544532158985565303983870 94
UVM_INFO @ 29954640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))' 2 test runs
kmac_sideload_invalid 68474821400682297351645235945724899768125454536804643809055271028130521282046 78
UVM_ERROR @ 3921162 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 3921162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_key_error 27002409272704766791673604260099822671608164480154982260576342816869479823066 78
UVM_ERROR @ 7030126 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 7030126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err) 1 test run
kmac_mubi 28433035577415390959973899170253464210448626804658454778172839898606314068770 78
UVM_INFO @ 672930262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---