Simulation Results: lc_ctrl/volatile_unlock_disabled

 
20/07/2026 20:41:39 DVSim: v1.49.12 sha: 54120d8 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.53 %
  • code
  • 92.03 %
  • assert
  • 96.25 %
  • func
  • 86.31 %
  • block
  • 96.52 %
  • line
  • 97.23 %
  • branch
  • 91.15 %
  • toggle
  • 84.49 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.000s 268.367us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 44.681us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 91.516us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 107.610us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 104.758us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 27.106us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 91.516us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 104.758us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 381.617us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.000s 5134.364us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 14.526us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 105.023us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 3.000s 1000.064us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.000s 6265.726us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 3.000s 1000.064us 1 1 100.00
lc_ctrl_prog_failure 3.000s 105.023us 1 1 100.00
lc_ctrl_errors 7.000s 6265.726us 1 1 100.00
lc_ctrl_security_escalation 4.000s 1152.061us 1 1 100.00
lc_ctrl_jtag_state_failure 21.000s 2838.947us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.000s 856.525us 1 1 100.00
lc_ctrl_jtag_errors 11.000s 2505.998us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.000s 404.821us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.000s 497.191us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.000s 856.525us 1 1 100.00
lc_ctrl_jtag_errors 11.000s 2505.998us 1 1 100.00
lc_ctrl_jtag_access 8.000s 1506.918us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.000s 1360.082us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 476.114us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 43.833us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.000s 1209.753us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.000s 482.904us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 58.578us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 239.509us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 160.244us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 17.000s 4134.492us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 46.038us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 92.000s 65576.588us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 26.841us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 36.448us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 36.448us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 44.681us 1 1 100.00
lc_ctrl_csr_rw 2.000s 91.516us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 104.758us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 62.855us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 44.681us 1 1 100.00
lc_ctrl_csr_rw 2.000s 91.516us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 104.758us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 62.855us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 321.867us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 795.077us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 795.077us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.000s 5134.364us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 1000.064us 1 1 100.00
lc_ctrl_sec_cm 4.000s 321.867us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 1000.064us 1 1 100.00
lc_ctrl_sec_cm 4.000s 321.867us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 3.000s 1000.064us 1 1 100.00
lc_ctrl_sec_cm 4.000s 321.867us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 3.000s 1000.064us 1 1 100.00
lc_ctrl_sec_cm 4.000s 321.867us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 1000.064us 1 1 100.00
lc_ctrl_sec_cm 4.000s 321.867us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 1000.064us 1 1 100.00
lc_ctrl_sec_cm 4.000s 321.867us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 3.000s 1000.064us 1 1 100.00
lc_ctrl_sec_cm 4.000s 321.867us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 3.000s 1000.064us 1 1 100.00
lc_ctrl_sec_cm 4.000s 321.867us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.000s 1152.061us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 381.617us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.000s 497.191us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 982.708us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 982.708us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.000s 1752.236us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 970.399us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 970.399us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 6.000s 1296.178us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 72276087202979043138985942725866870132886928006430138263038572509639221078782 910
UVM_INFO @ 1296177787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---