Simulation Results: lc_ctrl/volatile_unlock_enabled

 
20/07/2026 20:41:39 DVSim: v1.49.12 sha: 54120d8 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.22 %
  • code
  • 93.98 %
  • assert
  • 96.69 %
  • func
  • 85.99 %
  • block
  • 97.07 %
  • line
  • 97.63 %
  • branch
  • 92.56 %
  • toggle
  • 88.10 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 191.778us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 56.131us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 112.741us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 148.301us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 44.796us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 32.372us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 112.741us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 44.796us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 256.242us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 10.000s 2897.402us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 14.943us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 52.377us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.000s 597.289us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.000s 1055.682us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.000s 597.289us 1 1 100.00
lc_ctrl_prog_failure 3.000s 52.377us 1 1 100.00
lc_ctrl_errors 6.000s 1055.682us 1 1 100.00
lc_ctrl_security_escalation 6.000s 1318.703us 1 1 100.00
lc_ctrl_jtag_state_failure 12.000s 5329.563us 1 1 100.00
lc_ctrl_jtag_prog_failure 10.000s 911.191us 1 1 100.00
lc_ctrl_jtag_errors 14.000s 4859.591us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 5.000s 555.641us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.000s 3677.288us 1 1 100.00
lc_ctrl_jtag_prog_failure 10.000s 911.191us 1 1 100.00
lc_ctrl_jtag_errors 14.000s 4859.591us 1 1 100.00
lc_ctrl_jtag_access 6.000s 596.557us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.000s 1131.568us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 660.964us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 195.714us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.000s 389.317us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 8.000s 1096.426us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 33.075us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 299.710us 1 1 100.00
lc_ctrl_jtag_alert_test 1.000s 159.624us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.000s 2459.380us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 18.100us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 138.000s 8542.595us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 76.284us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 45.948us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 45.948us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 56.131us 1 1 100.00
lc_ctrl_csr_rw 2.000s 112.741us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 44.796us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 106.415us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 56.131us 1 1 100.00
lc_ctrl_csr_rw 2.000s 112.741us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 44.796us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 106.415us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 265.097us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 507.258us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 507.258us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 10.000s 2897.402us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 597.289us 1 1 100.00
lc_ctrl_sec_cm 4.000s 265.097us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 597.289us 1 1 100.00
lc_ctrl_sec_cm 4.000s 265.097us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 597.289us 1 1 100.00
lc_ctrl_sec_cm 4.000s 265.097us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 597.289us 1 1 100.00
lc_ctrl_sec_cm 4.000s 265.097us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 597.289us 1 1 100.00
lc_ctrl_sec_cm 4.000s 265.097us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 597.289us 1 1 100.00
lc_ctrl_sec_cm 4.000s 265.097us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 597.289us 1 1 100.00
lc_ctrl_sec_cm 4.000s 265.097us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.000s 597.289us 1 1 100.00
lc_ctrl_sec_cm 4.000s 265.097us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 1318.703us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 256.242us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.000s 3677.288us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.000s 327.646us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.000s 327.646us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.000s 559.458us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.000s 606.707us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.000s 606.707us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 19.000s 5287.623us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 7531716411985439437667587994618936213605513409173345905894592225259624474293 4556
UVM_INFO @ 5287622614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---