Simulation Results: mbx

 
20/07/2026 20:41:39 DVSim: v1.49.12 sha: 54120d8 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.48 %
  • code
  • 89.57 %
  • assert
  • 97.05 %
  • func
  • 84.82 %
  • block
  • 96.95 %
  • line
  • 96.91 %
  • branch
  • 92.07 %
  • toggle
  • 79.74 %
Validation stages
V1
100.00%
V2
72.73%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 76.000s 8938.751us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 17.473us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 11.610us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 8.000s 3161.510us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 104.819us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
mbx_csr_mem_rw_with_rand_reset 1.000s 205.338us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 11.610us 1 1 100.00
mbx_csr_aliasing 2.000s 104.819us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 6.000s 1163.508us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 1.000s 24.084us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 8.000s 1092.102us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 8.000s 764.884us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 65.402us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 21.695us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 3.000s 274.553us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 3.000s 274.553us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 17.473us 1 1 100.00
mbx_csr_rw 1.000s 11.610us 1 1 100.00
mbx_csr_aliasing 2.000s 104.819us 1 1 100.00
mbx_same_csr_outstanding 1.000s 37.740us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 17.473us 1 1 100.00
mbx_csr_rw 1.000s 11.610us 1 1 100.00
mbx_csr_aliasing 2.000s 104.819us 1 1 100.00
mbx_same_csr_outstanding 1.000s 37.740us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 475.071us 1 1 100.00
mbx_sec_cm 1.000s 31.174us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched 1 test run
mbx_stress 65336024572752631246215603503249084588209100758867313011291833002450942141538 138
UVM_INFO @ 1163508293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register 1 test run
mbx_stress_zero_delays 64287712127255401450667518497123836828426581408016075203615721336654362200094 89
UVM_INFO @ 24083833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 1 test run
mbx_tl_errors 31010570954057385576169964265405924768504166917383238922155082472933771011571 86
TL item was: req: (cip_tl_seq_item@22206) { a_addr: 'h6211c1f4 a_data: 'hc25ff886 a_mask: 'h1 a_size: 'h1 a_param: 'h0 a_source: 'ha4 a_opcode: 'h1 a_user: 'h271a4 d_param: 'h0 d_source: 'ha4 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 274553387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---