Simulation Results: otp_ctrl

 
20/07/2026 20:41:39 DVSim: v1.49.12 sha: 54120d8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 74.31 %
  • code
  • 72.68 %
  • assert
  • 93.99 %
  • func
  • 56.25 %
  • line
  • 87.51 %
  • branch
  • 84.22 %
  • cond
  • 85.94 %
  • toggle
  • 69.10 %
  • FSM
  • 36.65 %
Validation stages
V1
100.00%
V2
75.00%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.740s 61.517us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 16.880s 11512.494us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.830s 243.451us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.180s 49.032us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.940s 323.759us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 6.380s 516.955us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.070s 220.990us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.180s 49.032us 1 1 100.00
otp_ctrl_csr_aliasing 6.380s 516.955us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.350s 45.156us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.600s 163.459us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 142.590s 46428.318us 0 1 0.00
init_fail 0 1 0.00
otp_ctrl_init_fail 2.740s 925.219us 0 1 0.00
partition_check 2 2 100.00
otp_ctrl_background_chks 7.210s 902.734us 1 1 100.00
otp_ctrl_check_fail 4.950s 236.822us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 10.340s 3363.621us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 8.480s 1534.653us 1 1 100.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 7.980s 551.095us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 15.400s 797.871us 1 1 100.00
otp_ctrl_parallel_lc_esc 4.040s 150.636us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 36.440s 3993.129us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 4.920s 316.378us 1 1 100.00
test_access 0 1 0.00
otp_ctrl_test_access 3.590s 140.920us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 120.250s 62943.939us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.520s 719.140us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.940s 948.192us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 5.130s 2190.477us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 5.130s 2190.477us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.830s 243.451us 1 1 100.00
otp_ctrl_csr_rw 2.180s 49.032us 1 1 100.00
otp_ctrl_csr_aliasing 6.380s 516.955us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.240s 402.696us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.830s 243.451us 1 1 100.00
otp_ctrl_csr_rw 2.180s 49.032us 1 1 100.00
otp_ctrl_csr_aliasing 6.380s 516.955us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.240s 402.696us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 308.330s 21393.108us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 308.330s 21393.108us 1 1 100.00
otp_ctrl_tl_intg_err 21.740s 2693.706us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 308.330s 21393.108us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 308.330s 21393.108us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 21.740s 2693.706us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 16.880s 11512.494us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 16.880s 11512.494us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 308.330s 21393.108us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 308.330s 21393.108us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 308.330s 21393.108us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 308.330s 21393.108us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 308.330s 21393.108us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 308.330s 21393.108us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 308.330s 21393.108us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 308.330s 21393.108us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 308.330s 21393.108us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 308.330s 21393.108us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 308.330s 21393.108us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 308.330s 21393.108us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 308.330s 21393.108us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 308.330s 21393.108us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 308.330s 21393.108us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.040s 150.636us 1 1 100.00
otp_ctrl_sec_cm 308.330s 21393.108us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.040s 150.636us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.040s 150.636us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.040s 150.636us 1 1 100.00
otp_ctrl_macro_errs 4.920s 316.378us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.040s 150.636us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.040s 150.636us 1 1 100.00
otp_ctrl_sec_cm 308.330s 21393.108us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.040s 150.636us 1 1 100.00
otp_ctrl_sec_cm 308.330s 21393.108us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.040s 150.636us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.040s 150.636us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.040s 150.636us 1 1 100.00
otp_ctrl_macro_errs 4.920s 316.378us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.040s 150.636us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.040s 150.636us 1 1 100.00
otp_ctrl_sec_cm 308.330s 21393.108us 1 1 100.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 2.740s 925.219us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 4.950s 236.822us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 8.480s 1534.653us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 8.480s 1534.653us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 8.480s 1534.653us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 8.480s 1534.653us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 8.480s 1534.653us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 16.880s 11512.494us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 8.480s 1534.653us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 16.880s 11512.494us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 308.330s 21393.108us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 10.340s 3363.621us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 16.880s 11512.494us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 16.880s 11512.494us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 4.920s 316.378us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 92.450s 68976.151us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 3.170s 255.618us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 2 test runs
otp_ctrl_partition_walk 112675091774488196278038200746388805911002376472229011497972111043754953067654 160055
UVM_INFO @ 46428317855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 48636151010291392831556839928296299851399420653949488013735315556623346237439 1735
UVM_INFO @ 925218968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 2 test runs
otp_ctrl_low_freq_read 70788245191988255047115461192195376359072986388460165007076887177509776338466 89
UVM_INFO @ 68976150541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 56703044856269754863348534746862053171610104475194244764487019094100003356174 90
UVM_INFO @ 62943938591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:671) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 1 test run
otp_ctrl_parallel_key_req 87006569738746006387359860568741131528693830155968449064940715175496164528488 6347
UVM_INFO @ 551094964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 1 test run
otp_ctrl_test_access 100699920848061593201665151985262078431267862632714621906469867052223353530288 2290
UVM_INFO @ 140920364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:2213) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 20655629193227562026911469888346140681678288114880455925853726911922390991914 156
UVM_INFO @ 255618053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---