Simulation Results: rstmgr

 
20/07/2026 20:41:39 DVSim: v1.49.12 sha: 54120d8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.90 %
  • code
  • 99.21 %
  • assert
  • 98.72 %
  • func
  • 95.78 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.41 %
  • toggle
  • 99.52 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.440s 57.922us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.000s 64.594us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.950s 36.471us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.150s 82.089us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.250s 40.849us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.230s 67.408us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.950s 36.471us 1 1 100.00
rstmgr_csr_aliasing 1.250s 40.849us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.760s 130.113us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.360s 48.096us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.010s 40.865us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 6.120s 749.782us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 6.120s 749.782us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 6.120s 749.782us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 6.120s 749.782us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 13.830s 2290.917us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.100s 42.497us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.890s 42.536us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.890s 42.536us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.000s 64.594us 1 1 100.00
rstmgr_csr_rw 0.950s 36.471us 1 1 100.00
rstmgr_csr_aliasing 1.250s 40.849us 1 1 100.00
rstmgr_same_csr_outstanding 0.910s 38.291us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.000s 64.594us 1 1 100.00
rstmgr_csr_rw 0.950s 36.471us 1 1 100.00
rstmgr_csr_aliasing 1.250s 40.849us 1 1 100.00
rstmgr_same_csr_outstanding 0.910s 38.291us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 30.210s 6808.512us 1 1 100.00
rstmgr_tl_intg_err 4.370s 620.152us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 30.210s 6808.512us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 30.210s 6808.512us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 4.370s 620.152us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.010s 57.396us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.550s 465.749us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.000s 292.000us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 30.210s 6808.512us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.950s 36.471us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.950s 36.471us 1 1 100.00