Simulation Results

Simulation Results: rv_dm/use_dmi_interface

20/07/2026 20:41:39 DVSim: v1.49.12 sha: 54120d8 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
90.91 %

code
81.89 %

assert
96.59 %

func
94.24 %

block
92.85 %

line
93.51 %

branch
80.58 %

toggle
73.09 %

FSM
80.36 %

Validation stages

V1		96.30%
V2		78.26%
V2S		100.00%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	39.000s	4096.569us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	33.000s	449.713us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	30.000s	286.216us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	32.000s	5787.429us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	34.000s	473.545us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	34.000s	2725.729us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	40.000s	15726.790us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	30.000s	36.304us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	64.000s	70171.792us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	31.000s	268.375us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	32.000s	130.353us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	33.000s	332.394us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	34.000s	89.085us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	30.000s	599.414us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	31.000s	883.240us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	30.000s	62.502us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	32.000s	1275.414us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	31.000s	268.375us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	32.000s	225.437us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	31.000s	163.385us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	33.000s	332.394us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	32.000s	44.947us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	35.000s	213.890us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	31.000s	107.522us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	57.000s	18931.611us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	64.000s	3904.533us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	30.000s	303.751us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	64.000s	3904.533us	1	1	100.00
	rv_dm_csr_rw	31.000s	107.522us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	30.000s	68.647us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	31.000s	48.065us	1	1	100.00

18/23 passed

78.26 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	39.000s	4096.569us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	30.000s	190.095us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	30.000s	228.871us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	29.000s	150.352us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	30.000s	1079.817us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	38.000s	9218.761us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	30.000s	54.013us	0	1	0.00
bad_sba				1	1	100.00
	rv_dm_bad_sba_tl_access	32.000s	5100.751us	1	1	100.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	84.000s	135660.393us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	30.000s	295.583us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	37.000s	5336.352us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	32.000s	380.750us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	31.000s	61.838us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	37.000s	3934.309us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	63.000s	15751.484us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	30.000s	140.763us	1	1	100.00
stress_all				1	1	100.00
	rv_dm_stress_all	33.000s	3850.329us	1	1	100.00
alert_test				1	1	100.00
	rv_dm_alert_test	30.000s	187.523us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	31.000s	72.710us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	31.000s	72.710us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	64.000s	3904.533us	1	1	100.00
	rv_dm_csr_hw_reset	35.000s	213.890us	1	1	100.00
	rv_dm_csr_rw	31.000s	107.522us	1	1	100.00
	rv_dm_same_csr_outstanding	35.000s	656.599us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	64.000s	3904.533us	1	1	100.00
	rv_dm_csr_hw_reset	35.000s	213.890us	1	1	100.00
	rv_dm_csr_rw	31.000s	107.522us	1	1	100.00
	rv_dm_same_csr_outstanding	35.000s	656.599us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	33.000s	1281.287us	1	1	100.00
	rv_dm_tl_intg_err	41.000s	6485.427us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	41.000s	6485.427us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	37.000s	5336.352us	1	1	100.00
	rv_dm_debug_disabled	30.000s	133.523us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	37.000s	5336.352us	1	1	100.00
	rv_dm_debug_disabled	30.000s	133.523us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	39.000s	4096.569us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	31.000s	344.114us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	31.000s	247.225us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	31.000s	247.225us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	31.000s	344.114us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	35.000s	788.528us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	149.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				2 test runs
	rv_dm_sba_tl_access	30329593613080716303879452591872323872372703906291530842157488058470052737935	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23805
	rv_dm_autoincr_sba_tl_access	73606686725818103973106631917445128234446256101209549476803170282429497242043	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23865
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				2 test runs
	rv_dm_hart_unavail	13736493025645158486231393066125256466086892029168001008442556871083074678519	87	UVM_INFO @ 61837834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	114370470229738359780769699279038686767180291452711556955913156659975235219903	105	UVM_INFO @ 788528418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				1 test run
	rv_dm_delayed_resp_sba_tl_access	55295287491185930908478986534314120317242631719571624536451415091297314631503	107	UVM_INFO @ 54013341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				1 test run
	rv_dm_mem_tl_access_resuming	81603686402215654184169979892380847361866782941904594501701587023839569805044	87	UVM_INFO @ 89084706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				1 test run
	rv_dm_jtag_dmi_debug_disabled	80592813304931269703650694570895337082214649636958230459815995897849167733760	87	UVM_INFO @ 295583288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	43113434705643317047221691276552553534528876831339577329835524884685364086754	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---