Simulation Results: rv_timer

 
20/07/2026 20:41:39 DVSim: v1.49.12 sha: 54120d8 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 98.09 %
  • code
  • 95.85 %
  • assert
  • 98.42 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.26 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.000s 37.058us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 15.897us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 29.672us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 78.373us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 22.073us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 107.771us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 29.672us 1 1 100.00
rv_timer_csr_aliasing 1.000s 22.073us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.000s 687.741us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 2848.837us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 68.000s 226383.267us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 68.000s 226383.267us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 5.000s 4247.516us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 2.000s 48.549us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 12.640us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 3.000s 151.092us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 3.000s 151.092us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 15.897us 1 1 100.00
rv_timer_csr_rw 1.000s 29.672us 1 1 100.00
rv_timer_csr_aliasing 1.000s 22.073us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 19.976us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 15.897us 1 1 100.00
rv_timer_csr_rw 1.000s 29.672us 1 1 100.00
rv_timer_csr_aliasing 1.000s 22.073us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 19.976us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 44.909us 1 1 100.00
rv_timer_tl_intg_err 2.000s 131.243us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 2.000s 131.243us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.000s 61.533us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.000s 43.050us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
rv_timer_stress_all_with_rand_reset 14.000s 10207.753us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 79304358004710057620408649987482662452644857381713525601036228106820539527401 87
UVM_INFO @ 61532900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 44086230483665976577455565468798691452556326644925320142118706334271442836338 84
UVM_INFO @ 687741297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 54186622258530487507409505910865709652519245099036623711612633191490192772386 84
UVM_INFO @ 43049987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
rv_timer_stress_all_with_rand_reset 94651752022907799483289889683853269217495434476003070698445629637119488503167 238
UVM_INFO @ 10207752913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---