Simulation Results: spi_device/1r1w

 
20/07/2026 20:41:39 DVSim: v1.49.12 sha: 54120d8 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.52 %
  • code
  • 89.44 %
  • assert
  • 95.40 %
  • func
  • 71.73 %
  • block
  • 98.28 %
  • line
  • 98.58 %
  • branch
  • 96.86 %
  • toggle
  • 72.75 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 32.000s 2163.699us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.000s 88.702us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.000s 37.045us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 18.000s 4860.405us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 12.000s 2828.939us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.000s 40.786us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.000s 37.045us 1 1 100.00
spi_device_csr_aliasing 12.000s 2828.939us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 2.000s 23.288us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.000s 20.101us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 1.000s 22.742us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 1.000s 4.098us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 1.000s 4.671us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 6.000s 3723.276us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 6.000s 3723.276us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 17.000s 2573.593us 1 1 100.00
spi_device_tpm_sts_read 2.000s 24.591us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 39.000s 13054.366us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 7.000s 454.723us 1 1 100.00
spi_device_flash_all 73.000s 27069.869us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.000s 1225.643us 1 1 100.00
spi_device_flash_all 73.000s 27069.869us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.000s 1225.643us 1 1 100.00
spi_device_flash_all 73.000s 27069.869us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 73.000s 27069.869us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 9.000s 339.617us 1 1 100.00
spi_device_flash_all 73.000s 27069.869us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 9.000s 339.617us 1 1 100.00
spi_device_flash_all 73.000s 27069.869us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 9.000s 339.617us 1 1 100.00
spi_device_flash_all 73.000s 27069.869us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 9.000s 339.617us 1 1 100.00
spi_device_flash_all 73.000s 27069.869us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 9.000s 339.617us 1 1 100.00
spi_device_flash_all 73.000s 27069.869us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 9.000s 4354.825us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 61.000s 7153.060us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 61.000s 7153.060us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 61.000s 7153.060us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 11.000s 1494.348us 1 1 100.00
spi_device_read_buffer_direct 7.000s 8420.920us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 61.000s 7153.060us 1 1 100.00
spi_device_flash_all 73.000s 27069.869us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 73.000s 27069.869us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 73.000s 27069.869us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 5.000s 179.902us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 5.000s 179.902us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 75.000s 23759.488us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 32.000s 2163.699us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 131.000s 132367.660us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 172.000s 29300.203us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 19.800us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 2.000s 15.070us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.000s 194.350us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.000s 194.350us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.000s 88.702us 1 1 100.00
spi_device_csr_rw 2.000s 37.045us 1 1 100.00
spi_device_csr_aliasing 12.000s 2828.939us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 293.598us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.000s 88.702us 1 1 100.00
spi_device_csr_rw 2.000s 37.045us 1 1 100.00
spi_device_csr_aliasing 12.000s 2828.939us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 293.598us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 394.461us 1 1 100.00
spi_device_tl_intg_err 14.000s 4770.747us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 14.000s 4770.747us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 16574089697863735759514389465469348400185741621694873830055842645089491415579 87
UVM_ERROR @ 2973310 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[904] not found within the scope .
UVM_ERROR @ 2973310 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[904] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 49641297099989933019800836896340589965627562588215985905279525215677483452152 85
UVM_ERROR @ 1921505 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3d9 [1111011001] vs 0x0 [0])
UVM_ERROR @ 2001505 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x26e [1001101110] vs 0x0 [0])
UVM_ERROR @ 2047505 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2f9 [1011111001] vs 0x0 [0])
UVM_ERROR @ 2141505 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2ae [1010101110] vs 0x0 [0])