Simulation Results: spi_host

 
20/07/2026 20:41:39 DVSim: v1.49.12 sha: 54120d8 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.14 %
  • code
  • 94.83 %
  • assert
  • 95.09 %
  • func
  • 89.50 %
  • block
  • 96.74 %
  • line
  • 98.43 %
  • branch
  • 92.85 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 10.000s 1068.535us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 171.233us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 93.441us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 133.555us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 34.989us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 77.348us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 93.441us 1 1 100.00
spi_host_csr_aliasing 2.000s 34.989us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 17.344us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 42.075us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 60.339us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 129.322us 1 1 100.00
spi_host_error_cmd 1.000s 21.639us 1 1 100.00
spi_host_event 8.000s 1391.988us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 86.504us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 86.504us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 86.504us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 342.000s 26827.776us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 12.000s 898.570us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 59.099us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 86.504us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 86.504us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 10.000s 1068.535us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 10.000s 1068.535us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 1.000s 51.653us 1 1 100.00
spien 1 1 100.00
spi_host_spien 3.000s 410.491us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 42.000s 6318.774us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 311.764us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 129.322us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 38.421us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 2.000s 47.203us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 31.584us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 31.584us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 171.233us 1 1 100.00
spi_host_csr_rw 1.000s 93.441us 1 1 100.00
spi_host_csr_aliasing 2.000s 34.989us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 35.477us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 171.233us 1 1 100.00
spi_host_csr_rw 1.000s 93.441us 1 1 100.00
spi_host_csr_aliasing 2.000s 34.989us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 35.477us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 97.103us 1 1 100.00
spi_host_sec_cm 1.000s 63.826us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 97.103us 1 1 100.00