Simulation Results: sram_ctrl/main

 
20/07/2026 20:41:39 DVSim: v1.49.12 sha: 54120d8 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.79 %
  • code
  • 95.40 %
  • assert
  • 97.96 %
  • func
  • 94.00 %
  • block
  • 95.77 %
  • line
  • 96.46 %
  • branch
  • 93.53 %
  • toggle
  • 91.60 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 6.000s 705.216us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 17.012us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 19.219us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 33.493us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.305us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 4246.028us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 19.219us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.305us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 248.000s 123755.740us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 85.000s 2525.155us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 17.000s 6896.458us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 178.000s 5236.635us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 115.000s 5771.612us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 61.000s 15943.182us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 48.000s 17747.014us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 27.000s 7482.718us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 704.126us 1 1 100.00
sram_ctrl_partial_access_b2b 184.000s 40916.741us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 7.000s 2536.197us 0 1 0.00
sram_ctrl_throughput_w_partial_write 4.000s 4717.831us 0 1 0.00
sram_ctrl_throughput_w_readback 5.000s 668.676us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 10.000s 6140.292us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 3712.692us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 124.000s 164453.336us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 11.379us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 161.134us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 161.134us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 17.012us 1 1 100.00
sram_ctrl_csr_rw 1.000s 19.219us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.305us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 71.434us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 17.012us 1 1 100.00
sram_ctrl_csr_rw 1.000s 19.219us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 20.305us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 71.434us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 9302.775us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 847.573us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 255.356us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 847.573us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 255.356us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 6140.292us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 6140.292us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 19.219us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 27.000s 7482.718us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 27.000s 7482.718us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 27.000s 7482.718us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 48.000s 17747.014us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 6644.960us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 9302.775us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 6.000s 2685.329us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 705.216us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 705.216us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 27.000s 7482.718us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 847.573us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 48.000s 17747.014us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 847.573us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 847.573us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 6.000s 705.216us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 847.573us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 34.000s 17828.261us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 76895549237542502732266274295336242957190466439220947689239078746973332314634 86
UVM_INFO @ 2536197248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 5170122594822334184686625380467722281831440444697407307155496316087830246296 86
UVM_INFO @ 4717831204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 49153831929637980192377054500169720429092740180674361773213606146332982030348 86
UVM_INFO @ 668676084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---