Simulation Results: uart

 
20/07/2026 20:41:39 DVSim: v1.49.12 sha: 54120d8 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.80 %
  • code
  • 96.60 %
  • assert
  • 97.12 %
  • func
  • 90.69 %
  • block
  • 99.08 %
  • line
  • 99.52 %
  • branch
  • 98.34 %
  • toggle
  • 88.53 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.000s 658.669us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 26.537us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 2.000s 65.824us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.000s 567.785us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 2.000s 116.852us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 27.772us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 2.000s 65.824us 1 1 100.00
uart_csr_aliasing 2.000s 116.852us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 7.000s 22054.527us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.000s 658.669us 1 1 100.00
uart_tx_rx 7.000s 22054.527us 1 1 100.00
parity_error 2 2 100.00
uart_intr 9.000s 9949.189us 1 1 100.00
uart_rx_parity_err 12.000s 30229.995us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 7.000s 22054.527us 1 1 100.00
uart_intr 9.000s 9949.189us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 36.000s 155564.093us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 58.000s 56919.220us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 65.000s 35384.068us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 9.000s 9949.189us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 9.000s 9949.189us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 9.000s 9949.189us 1 1 100.00
perf 1 1 100.00
uart_perf 62.000s 15882.562us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 4.000s 1529.085us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 4.000s 1529.085us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 11.000s 8879.651us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.000s 3197.796us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.000s 841.229us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 4.000s 4062.408us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 147.000s 47306.602us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 35.000s 126106.258us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 99.922us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 19.395us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 268.079us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 268.079us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 26.537us 1 1 100.00
uart_csr_rw 2.000s 65.824us 1 1 100.00
uart_csr_aliasing 2.000s 116.852us 1 1 100.00
uart_same_csr_outstanding 1.000s 69.877us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 26.537us 1 1 100.00
uart_csr_rw 2.000s 65.824us 1 1 100.00
uart_csr_aliasing 2.000s 116.852us 1 1 100.00
uart_same_csr_outstanding 1.000s 69.877us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 482.705us 1 1 100.00
uart_tl_intg_err 1.000s 72.410us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.000s 72.410us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 22.000s 2867.257us 1 1 100.00