Simulation Results: ac_range_check

 
21/07/2026 19:39:46 DVSim: v1.49.12 sha: b583fba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.64 %
  • code
  • 92.55 %
  • assert
  • 97.75 %
  • func
  • 57.61 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 79.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 20.000s 509.876us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 30.000s 738.922us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 134.650us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 47.971us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 21.000s 2825.911us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 19.000s 2834.695us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 1.000s 53.797us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 47.971us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 2834.695us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 251.458us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 29.000s 1692.494us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 160.000s 4069.637us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 1.000s 34.443us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 2.000s 40.197us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 4.000s 151.694us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 4.000s 151.694us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 134.650us 1 1 100.00
ac_range_check_csr_rw 2.000s 47.971us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 2834.695us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 417.345us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 134.650us 1 1 100.00
ac_range_check_csr_rw 2.000s 47.971us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 2834.695us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 417.345us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 843.965us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 843.965us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 843.965us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 843.965us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 54.000s 5244.045us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 2.000s 22.051us 1 1 100.00
ac_range_check_tl_intg_err 5.000s 229.679us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 272.000s 7726.523us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 31.000s 1788.856us 1 1 100.00