Simulation Results: aes/gcm_masked

 
21/07/2026 19:39:46 DVSim: v1.49.12 sha: b583fba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.64 %
  • code
  • 95.14 %
  • assert
  • 98.29 %
  • func
  • 66.51 %
  • block
  • 95.77 %
  • line
  • 97.51 %
  • branch
  • 89.50 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
89.47%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 123.066us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 131.156us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 59.604us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 68.761us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 248.010us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 166.324us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 96.333us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 68.761us 1 1 100.00
aes_csr_aliasing 2.000s 166.324us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 131.156us 1 1 100.00
aes_config_error 7.000s 951.880us 1 1 100.00
aes_stress 4.000s 153.731us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 131.156us 1 1 100.00
aes_config_error 7.000s 951.880us 1 1 100.00
aes_stress 4.000s 153.731us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 153.731us 1 1 100.00
aes_b2b 7.000s 1116.511us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 153.731us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 131.156us 1 1 100.00
aes_config_error 7.000s 951.880us 1 1 100.00
aes_stress 4.000s 153.731us 1 1 100.00
aes_alert_reset 1616.000s 200000.000us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 98.794us 1 1 100.00
aes_config_error 7.000s 951.880us 1 1 100.00
aes_alert_reset 1616.000s 200000.000us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 79.554us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 344.872us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 6.000s 2012.475us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 1616.000s 200000.000us 0 1 0.00
stress 1 1 100.00
aes_stress 4.000s 153.731us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 153.731us 1 1 100.00
aes_sideload 5.000s 327.495us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 465.494us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 8.000s 235.423us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 4.000s 140.115us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 56.730us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 84.655us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 84.655us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 59.604us 1 1 100.00
aes_csr_rw 1.000s 68.761us 1 1 100.00
aes_csr_aliasing 2.000s 166.324us 1 1 100.00
aes_same_csr_outstanding 2.000s 138.075us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 59.604us 1 1 100.00
aes_csr_rw 1.000s 68.761us 1 1 100.00
aes_csr_aliasing 2.000s 166.324us 1 1 100.00
aes_same_csr_outstanding 2.000s 138.075us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 4.000s 222.994us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 6.000s 686.619us 0 1 0.00
aes_control_fi 1.000s 60.440us 1 1 100.00
aes_cipher_fi 2.000s 52.453us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 129.286us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 129.286us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 129.286us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 129.286us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 334.363us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 6.000s 631.483us 1 1 100.00
aes_tl_intg_err 2.000s 147.528us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 147.528us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 1616.000s 200000.000us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 129.286us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 129.286us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 131.156us 1 1 100.00
aes_stress 4.000s 153.731us 1 1 100.00
aes_alert_reset 1616.000s 200000.000us 0 1 0.00
aes_core_fi 3.000s 400.725us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 4.000s 140.115us 1 1 100.00
aes_config_error 7.000s 951.880us 1 1 100.00
aes_stress 4.000s 153.731us 1 1 100.00
aes_core_fi 3.000s 400.725us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 129.286us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 79.636us 1 1 100.00
aes_stress 4.000s 153.731us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 153.731us 1 1 100.00
aes_sideload 5.000s 327.495us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 79.636us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 79.636us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 79.636us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 79.636us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 79.636us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 153.731us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 153.731us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 6.000s 686.619us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 6.000s 686.619us 0 1 0.00
aes_control_fi 1.000s 60.440us 1 1 100.00
aes_cipher_fi 2.000s 52.453us 1 1 100.00
aes_ctr_fi 2.000s 62.002us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 6.000s 686.619us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 6.000s 686.619us 0 1 0.00
aes_control_fi 1.000s 60.440us 1 1 100.00
aes_cipher_fi 2.000s 52.453us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 52.453us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 6.000s 686.619us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 6.000s 686.619us 0 1 0.00
aes_control_fi 1.000s 60.440us 1 1 100.00
aes_ctr_fi 2.000s 62.002us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 6.000s 686.619us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 6.000s 686.619us 0 1 0.00
aes_control_fi 1.000s 60.440us 1 1 100.00
aes_cipher_fi 2.000s 52.453us 1 1 100.00
aes_ctr_fi 2.000s 62.002us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 1616.000s 200000.000us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 6.000s 686.619us 0 1 0.00
aes_control_fi 1.000s 60.440us 1 1 100.00
aes_cipher_fi 2.000s 52.453us 1 1 100.00
aes_ctr_fi 2.000s 62.002us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 6.000s 686.619us 0 1 0.00
aes_control_fi 1.000s 60.440us 1 1 100.00
aes_cipher_fi 2.000s 52.453us 1 1 100.00
aes_ctr_fi 2.000s 62.002us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 6.000s 686.619us 0 1 0.00
aes_control_fi 1.000s 60.440us 1 1 100.00
aes_ctr_fi 2.000s 62.002us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 2.000s 85.231us 1 1 100.00
aes_fi 6.000s 686.619us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 6.000s 686.619us 0 1 0.00
aes_control_fi 1.000s 60.440us 1 1 100.00
aes_cipher_fi 2.000s 52.453us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 1.000s 21.999us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_reseed 96706962138260357782236109961248004377746221675139952079563048557112510023524 5725
UVM_INFO @ 222994402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 41382509557831857440554190044243333410947765274209305109000323391737178398286 54738
UVM_INFO @ 235423322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
aes_alert_reset 87658963228807482447764555226164382666549512417929746060335450394148614636357 16665254
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 7820047695202328828104419143013826693250267980720715129330923400319929646501 23633
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 4
----| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 5911842318422974836759216139871457145369374758558902005940410333115574995158 138
UVM_INFO @ 21999110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---