Simulation Results: clkmgr

 
21/07/2026 19:39:46 DVSim: v1.49.12 sha: b583fba json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.17 %
  • code
  • 67.05 %
  • assert
  • 88.22 %
  • func
  • 64.23 %
  • line
  • 81.10 %
  • branch
  • 85.86 %
  • cond
  • 74.03 %
  • toggle
  • 94.25 %
  • FSM
  • 0.00 %
Validation stages
V1
33.33%
V2
61.54%
V2S
12.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.950s 26.047us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.010s 23.920us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.680s 2.479us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 1.000s 24.454us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.740s 3.447us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.800s 13.615us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.680s 2.479us 0 1 0.00
clkmgr_csr_aliasing 0.740s 3.447us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.730s 129.734us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.160s 24.583us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.870s 15.160us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.950s 26.047us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.860s 31.316us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.770s 3.208us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.860s 31.316us 0 1 0.00
stress_all 1 1 100.00
clkmgr_stress_all 0.960s 38.632us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 1.030s 17.816us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 6.540s 638.954us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 6.540s 638.954us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 1.010s 23.920us 1 1 100.00
clkmgr_csr_rw 0.680s 2.479us 0 1 0.00
clkmgr_csr_aliasing 0.740s 3.447us 0 1 0.00
clkmgr_same_csr_outstanding 0.710s 8.442us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 1.010s 23.920us 1 1 100.00
clkmgr_csr_rw 0.680s 2.479us 0 1 0.00
clkmgr_csr_aliasing 0.740s 3.447us 0 1 0.00
clkmgr_same_csr_outstanding 0.710s 8.442us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 0.730s 15.224us 0 1 0.00
clkmgr_tl_intg_err 0.610s 2.764us 0 1 0.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 1852.190s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 1852.190s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 1852.190s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 1852.190s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 1.110s 66.389us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.610s 2.764us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.860s 31.316us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.770s 3.208us 0 1 0.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 1852.190s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.840s 20.131us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.680s 2.479us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.730s 15.224us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.680s 2.479us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.680s 2.479us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.730s 15.224us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.820s 24.604us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 3.830s 267.906us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 3 test runs
clkmgr_shadow_reg_errors_with_csr_rw 8644568387850454860414537681903865867358013526765339991773266524236641061518 75
UVM_INFO @ 66388932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 16385009702981003948387853652152351974521559002010640916288353977424635637700 75
UVM_INFO @ 2478543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 49930550026855756855436964320359442307537875315752193882641640914384603169793 76
UVM_INFO @ 13614754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 82102738177222545427986899450081518163549230169443689524851007306369470747451 76
UVM_INFO @ 31315547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 68954207849546208696506636651003737365948297506258616628411736659442851212603 195
UVM_INFO @ 267906049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 2 test runs
clkmgr_tl_intg_err 106377653973008663853856158546225371169611061509365734463322960108759388248586 78
UVM_INFO @ 2764031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 115465756693208612217543740009883142666146733915029073537472510175723779624186 75
UVM_INFO @ 3446747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 1 test run
clkmgr_frequency_timeout 43953509609818565649056092129706293702018884880739728890981015563386871058917 78
UVM_INFO @ 3208498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed 1 test run
clkmgr_regwen 71535901582198898243962929605163538040072056078112827332255524958126181196938 74
UVM_INFO @ 24603636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 56191607349362395179202286178442734838134738695278836698718378846607243736623 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 78609278113733767747636763740142518822146973862596223970004490757551350968515 82
UVM_INFO @ 15223797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 70697831176592199199195796361045640543018186539393113048407480391448176980029 75
UVM_INFO @ 24454264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 20742793198961250017720002312184903739567029740810701626131660382852728870851 75
UVM_INFO @ 8442244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---