Simulation Results: csrng

 
21/07/2026 19:39:46 DVSim: v1.49.12 sha: b583fba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.42 %
  • code
  • 92.22 %
  • assert
  • 93.23 %
  • func
  • 70.81 %
  • block
  • 96.82 %
  • line
  • 97.62 %
  • branch
  • 92.18 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 61.725us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 36.063us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 73.923us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 19.000s 1339.654us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 61.146us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 114.799us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 73.923us 1 1 100.00
csrng_csr_aliasing 3.000s 61.146us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 3.000s 74.463us 1 1 100.00
alerts 1 1 100.00
csrng_alert 23.000s 2321.883us 1 1 100.00
err 1 1 100.00
csrng_err 1.000s 39.515us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 522.000s 65605.461us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 522.000s 65605.461us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 73.000s 4099.883us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 24.122us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 51.338us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 9.000s 758.853us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 9.000s 758.853us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 36.063us 1 1 100.00
csrng_csr_rw 2.000s 73.923us 1 1 100.00
csrng_csr_aliasing 3.000s 61.146us 1 1 100.00
csrng_same_csr_outstanding 3.000s 95.430us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 36.063us 1 1 100.00
csrng_csr_rw 2.000s 73.923us 1 1 100.00
csrng_csr_aliasing 3.000s 61.146us 1 1 100.00
csrng_same_csr_outstanding 3.000s 95.430us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 4.000s 92.117us 1 1 100.00
csrng_tl_intg_err 12.000s 869.564us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 2.000s 5.947us 0 1 0.00
csrng_csr_rw 2.000s 73.923us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 23.000s 2321.883us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 73.000s 4099.883us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 3.000s 74.463us 1 1 100.00
csrng_err 1.000s 39.515us 1 1 100.00
csrng_sec_cm 4.000s 92.117us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 3.000s 74.463us 1 1 100.00
csrng_err 1.000s 39.515us 1 1 100.00
csrng_sec_cm 4.000s 92.117us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 3.000s 74.463us 1 1 100.00
csrng_err 1.000s 39.515us 1 1 100.00
csrng_sec_cm 4.000s 92.117us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 3.000s 74.463us 1 1 100.00
csrng_err 1.000s 39.515us 1 1 100.00
csrng_sec_cm 4.000s 92.117us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 3.000s 74.463us 1 1 100.00
csrng_err 1.000s 39.515us 1 1 100.00
csrng_sec_cm 4.000s 92.117us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 23.000s 2321.883us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 3.000s 74.463us 1 1 100.00
csrng_err 1.000s 39.515us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 73.000s 4099.883us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 23.000s 2321.883us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 12.000s 869.564us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 3.000s 74.463us 1 1 100.00
csrng_err 1.000s 39.515us 1 1 100.00
csrng_sec_cm 4.000s 92.117us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 3.000s 74.463us 1 1 100.00
csrng_err 1.000s 39.515us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 3.000s 74.463us 1 1 100.00
csrng_err 1.000s 39.515us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 3.000s 74.463us 1 1 100.00
csrng_err 1.000s 39.515us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 3.000s 74.463us 1 1 100.00
csrng_err 1.000s 39.515us 1 1 100.00
csrng_sec_cm 4.000s 92.117us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 3.000s 74.463us 1 1 100.00
csrng_err 1.000s 39.515us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3602.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 1 test run
csrng_regwen 97480987252487567220955599787545569785628570485357878738708465318798175152135 99
UVM_INFO @ 5946961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 87029545265765758935894426052982617026826414241821168211290265994027729018034 None