Simulation Results: edn/edn1

 
21/07/2026 19:39:46 DVSim: v1.49.12 sha: b583fba json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.91 %
  • code
  • 82.68 %
  • assert
  • 98.44 %
  • func
  • 79.62 %
  • line
  • 97.88 %
  • branch
  • 92.64 %
  • cond
  • 90.00 %
  • toggle
  • 87.42 %
  • FSM
  • 45.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.790s 60.096us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.750s 35.140us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.750s 53.144us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.090s 319.791us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.010s 78.349us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.480s 97.597us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.750s 53.144us 1 1 100.00
edn_csr_aliasing 1.010s 78.349us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.080s 26.459us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.080s 26.459us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.080s 26.459us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.350s 21.675us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.980s 101.290us 1 1 100.00
errs 1 1 100.00
edn_err 1.140s 28.471us 1 1 100.00
disable 2 2 100.00
edn_disable 0.910s 34.141us 1 1 100.00
edn_disable_auto_req_mode 1.030s 34.592us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.370s 87.101us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.770s 15.601us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.820s 18.910us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.720s 393.570us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.720s 393.570us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.750s 35.140us 1 1 100.00
edn_csr_rw 0.750s 53.144us 1 1 100.00
edn_csr_aliasing 1.010s 78.349us 1 1 100.00
edn_same_csr_outstanding 0.900s 42.154us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.750s 35.140us 1 1 100.00
edn_csr_rw 0.750s 53.144us 1 1 100.00
edn_csr_aliasing 1.010s 78.349us 1 1 100.00
edn_same_csr_outstanding 0.900s 42.154us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.840s 765.901us 1 1 100.00
edn_tl_intg_err 1.430s 479.923us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.820s 48.937us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.980s 101.290us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.840s 765.901us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.840s 765.901us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.840s 765.901us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.840s 765.901us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.980s 101.290us 1 1 100.00
edn_sec_cm 3.840s 765.901us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.980s 101.290us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.430s 479.923us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 80.770s 11786.435us 1 1 100.00