Simulation Results: hmac

 
21/07/2026 19:39:46 DVSim: v1.49.12 sha: b583fba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.01 %
  • code
  • 96.00 %
  • assert
  • 97.17 %
  • func
  • 28.85 %
  • block
  • 97.51 %
  • line
  • 98.44 %
  • branch
  • 93.76 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 6.000s 720.162us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 30.730us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 110.122us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 14.000s 3439.180us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.000s 1186.938us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 92.535us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 110.122us 1 1 100.00
hmac_csr_aliasing 6.000s 1186.938us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 79.000s 3213.188us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 5.000s 119.273us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 14.000s 255.509us 1 1 100.00
hmac_test_sha384_vectors 25.000s 1414.118us 1 1 100.00
hmac_test_sha512_vectors 31.000s 1335.896us 1 1 100.00
hmac_test_hmac256_vectors 8.000s 961.729us 1 1 100.00
hmac_test_hmac384_vectors 10.000s 344.980us 1 1 100.00
hmac_test_hmac512_vectors 14.000s 1751.766us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 24.000s 2227.383us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 266.000s 8074.154us 1 1 100.00
error 1 1 100.00
hmac_error 85.000s 10520.946us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 44.000s 68296.057us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 6.000s 720.162us 1 1 100.00
hmac_long_msg 79.000s 3213.188us 1 1 100.00
hmac_back_pressure 5.000s 119.273us 1 1 100.00
hmac_datapath_stress 266.000s 8074.154us 1 1 100.00
hmac_burst_wr 24.000s 2227.383us 1 1 100.00
hmac_stress_all 439.000s 675867.840us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 6.000s 720.162us 1 1 100.00
hmac_long_msg 79.000s 3213.188us 1 1 100.00
hmac_back_pressure 5.000s 119.273us 1 1 100.00
hmac_datapath_stress 266.000s 8074.154us 1 1 100.00
hmac_wipe_secret 44.000s 68296.057us 1 1 100.00
hmac_test_sha256_vectors 14.000s 255.509us 1 1 100.00
hmac_test_sha384_vectors 25.000s 1414.118us 1 1 100.00
hmac_test_sha512_vectors 31.000s 1335.896us 1 1 100.00
hmac_test_hmac256_vectors 8.000s 961.729us 1 1 100.00
hmac_test_hmac384_vectors 10.000s 344.980us 1 1 100.00
hmac_test_hmac512_vectors 14.000s 1751.766us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 6.000s 720.162us 1 1 100.00
hmac_long_msg 79.000s 3213.188us 1 1 100.00
hmac_back_pressure 5.000s 119.273us 1 1 100.00
hmac_datapath_stress 266.000s 8074.154us 1 1 100.00
hmac_burst_wr 24.000s 2227.383us 1 1 100.00
hmac_error 85.000s 10520.946us 1 1 100.00
hmac_wipe_secret 44.000s 68296.057us 1 1 100.00
hmac_test_sha256_vectors 14.000s 255.509us 1 1 100.00
hmac_test_sha384_vectors 25.000s 1414.118us 1 1 100.00
hmac_test_sha512_vectors 31.000s 1335.896us 1 1 100.00
hmac_test_hmac256_vectors 8.000s 961.729us 1 1 100.00
hmac_test_hmac384_vectors 10.000s 344.980us 1 1 100.00
hmac_test_hmac512_vectors 14.000s 1751.766us 1 1 100.00
hmac_stress_all 439.000s 675867.840us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 439.000s 675867.840us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 18.519us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 2.000s 12.101us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 4.000s 139.782us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 4.000s 139.782us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 30.730us 1 1 100.00
hmac_csr_rw 1.000s 110.122us 1 1 100.00
hmac_csr_aliasing 6.000s 1186.938us 1 1 100.00
hmac_same_csr_outstanding 2.000s 66.154us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 30.730us 1 1 100.00
hmac_csr_rw 1.000s 110.122us 1 1 100.00
hmac_csr_aliasing 6.000s 1186.938us 1 1 100.00
hmac_same_csr_outstanding 2.000s 66.154us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 574.837us 1 1 100.00
hmac_tl_intg_err 4.000s 276.762us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 4.000s 276.762us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 6.000s 720.162us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.000s 96.275us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 78.000s 22495.374us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.000s 489.768us 1 1 100.00