Simulation Results

Simulation Results: i2c

21/07/2026 19:39:46 DVSim: v1.49.12 sha: b583fba json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
88.38 %

code
86.46 %

assert
97.46 %

func
81.22 %

block
96.28 %

line
95.65 %

branch
93.35 %

toggle
72.68 %

FSM
84.17 %

Validation stages

V1		100.00%
V2		85.37%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	168.000s	1069.500us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	11.000s	1161.450us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	2.000s	66.084us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	55.670us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.000s	334.444us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	102.144us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	2.000s	88.998us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	55.670us	1	1	100.00
	i2c_csr_aliasing	2.000s	102.144us	1	1	100.00

35/41 passed

85.37 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.000s	143.310us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	3600.000s	0.000us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	38.000s	6458.836us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	2.000s	29.647us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	3109.000s	13732.840us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	1678.000s	2550.421us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	98.993us	1	1	100.00
	i2c_host_fifo_fmt_empty	83.000s	1000.430us	1	1	100.00
	i2c_host_fifo_reset_rx	9.000s	1297.924us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	822.000s	4769.303us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	10.000s	1358.968us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	2.000s	74.011us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	4.000s	2356.061us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	25.000s	6377.422us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	5.000s	774.130us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	11.000s	1953.320us	1	1	100.00
	i2c_target_intr_smoke	4.000s	903.474us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	596.419us	1	1	100.00
	i2c_target_fifo_reset_tx	2.000s	736.711us	1	1	100.00
target_fifo_full				2	3	66.67
	i2c_target_stress_wr	3601.000s	0.000us	0	1	0.00
	i2c_target_stress_rd	11.000s	1953.320us	1	1	100.00
	i2c_target_intr_stress_wr	3143.000s	16733.457us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	7.000s	2617.415us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	371.000s	1265.905us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	6.000s	1030.802us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	20.000s	10247.572us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.000s	370.732us	1	1	100.00
	i2c_target_fifo_watermarks_tx	3.000s	432.733us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	38.000s	6458.836us	1	1	100.00
	i2c_host_perf_precise	1.000s	100.780us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	10.000s	1358.968us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.000s	320.528us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	4.000s	505.636us	1	1	100.00
	i2c_target_nack_acqfull_addr	4.000s	510.568us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	126.691us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	6.000s	343.131us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	4.000s	506.522us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	2.000s	43.083us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	6.000s	25.630us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.000s	23.886us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.000s	23.886us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	66.084us	1	1	100.00
	i2c_csr_rw	1.000s	55.670us	1	1	100.00
	i2c_csr_aliasing	2.000s	102.144us	1	1	100.00
	i2c_same_csr_outstanding	1.000s	44.063us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	66.084us	1	1	100.00
	i2c_csr_rw	1.000s	55.670us	1	1	100.00
	i2c_csr_aliasing	2.000s	102.144us	1	1	100.00
	i2c_same_csr_outstanding	1.000s	44.063us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.000s	307.732us	1	1	100.00
	i2c_sec_cm	1.000s	68.473us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.000s	307.732us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	8.000s	1560.990us	1
target_error_intr				1
	i2c_target_unexp_stop	2.000s	384.052us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	5.000s	926.269us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	98152947904577123691307543073050789356679989998340464609449307067058746236163	97	UVM_INFO @ 143310138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	26308354445332186731507775018599648508098800750998333411328679596354682275044	111	UVM_INFO @ 926269443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				2 test runs
	i2c_host_stress_all	77574961548271152250791365182226953557644094213210571122109428860382016978107	None
	i2c_target_stress_wr	98343072921833971696753780408504278842978105726335010666633429235375446738050	None
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	83926853071085677514559896944736109655534339742310862339173602852675853158030	93	UVM_INFO @ 2356060659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	77950157488929174952550077563735326727540003458469957099802703405020585337520	87	UVM_INFO @ 384052229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	30109744362006460657282167060193291242158461855626433904972790335646575511971	88	UVM_INFO @ 10247572128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	53385071027077692409025620350912734076233337732203830771635754982056345428986	106	UVM_INFO @ 1560990290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:629) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead				1 test run
	i2c_host_mode_toggle	110041582781467318235610785274369786790153036419675422787857131881989141627309	96	--> EXP: --------------------------------------------------- Name Type Size Value ---------------------------------------------------