Simulation Results: kmac/unmasked

 
21/07/2026 19:39:46 DVSim: v1.49.12 sha: b583fba json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.15 %
  • code
  • 66.73 %
  • assert
  • 96.50 %
  • func
  • 74.23 %
  • line
  • 92.78 %
  • branch
  • 87.05 %
  • cond
  • 84.92 %
  • toggle
  • 27.30 %
  • FSM
  • 41.61 %
Validation stages
V1
100.00%
V2
72.41%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 24.800s 11092.454us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.000s 48.342us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.250s 30.800us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 16.550s 11155.749us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 8.030s 3213.521us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 2.020s 333.754us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.250s 30.800us 1 1 100.00
kmac_csr_aliasing 8.030s 3213.521us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.730s 34.024us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.270s 47.918us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 1726.280s 332918.127us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 579.770s 106668.751us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 34.550s 6699.250us 1 1 100.00
kmac_test_vectors_sha3_256 1374.700s 103987.039us 1 1 100.00
kmac_test_vectors_sha3_384 1401.700s 84236.732us 1 1 100.00
kmac_test_vectors_sha3_512 12.660s 1433.503us 1 1 100.00
kmac_test_vectors_shake_128 174.190s 14684.205us 1 1 100.00
kmac_test_vectors_shake_256 320.800s 83016.084us 1 1 100.00
kmac_test_vectors_kmac 2.150s 165.867us 1 1 100.00
kmac_test_vectors_kmac_xof 2.300s 220.183us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 12.080s 279.300us 1 1 100.00
app 0 1 0.00
kmac_app 3.670s 251.128us 0 1 0.00
app_with_partial_data 0 1 0.00
kmac_app_with_partial_data 1.930s 999.190us 0 1 0.00
entropy_refresh 0 1 0.00
kmac_entropy_refresh 0.970s 27.461us 0 1 0.00
error 0 1 0.00
kmac_error 1.940s 84.899us 0 1 0.00
key_error 0 1 0.00
kmac_key_error 1.380s 70.047us 0 1 0.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 1.280s 110.160us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 24.620s 1830.810us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 3.640s 184.277us 1 1 100.00
entropy_ready_error 0 1 0.00
kmac_entropy_ready_error 1.110s 3.220us 0 1 0.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.210s 32.125us 1 1 100.00
stress_all 0 1 0.00
kmac_stress_all 634.830s 32746.476us 0 1 0.00
intr_test 1 1 100.00
kmac_intr_test 0.880s 34.454us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.140s 48.077us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 3.070s 361.407us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 3.070s 361.407us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.000s 48.342us 1 1 100.00
kmac_csr_rw 1.250s 30.800us 1 1 100.00
kmac_csr_aliasing 8.030s 3213.521us 1 1 100.00
kmac_same_csr_outstanding 1.580s 100.613us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.000s 48.342us 1 1 100.00
kmac_csr_rw 1.250s 30.800us 1 1 100.00
kmac_csr_aliasing 8.030s 3213.521us 1 1 100.00
kmac_same_csr_outstanding 1.580s 100.613us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.920s 337.341us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.920s 337.341us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.920s 337.341us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.920s 337.341us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 4.060s 479.794us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 59.580s 6623.265us 1 1 100.00
kmac_tl_intg_err 1.950s 218.608us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 1.950s 218.608us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.210s 32.125us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 24.800s 11092.454us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 12.080s 279.300us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.920s 337.341us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 59.580s 6623.265us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 59.580s 6623.265us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 59.580s 6623.265us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 24.800s 11092.454us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.210s 32.125us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 59.580s 6623.265us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 0 1 0.00
kmac_mubi 9.640s 219.499us 0 1 0.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 24.800s 11092.454us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 77.820s 1590.480us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] 6 test runs
kmac_app 87748268908835569045376096404711603837726858117432642524909514233222294431746 78
UVM_INFO @ 251128422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app_with_partial_data 62958449393190943722811714971231960787327737148274675545558545148231137489301 77
UVM_INFO @ 999189793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_refresh 6622035797628872286985095774671692851225536892869243226830670348182122839911 77
UVM_INFO @ 27460607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_error 100124145448626356814149076114496412677006925445427495012326771038838613953628 78
UVM_INFO @ 84898768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_ready_error 26885473649978672591696531457151687267410553720018629144037850442664410169424 77
UVM_INFO @ 3220208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 30708859604660715284992811538288173094724415613787463920258717733459719404745 145
UVM_INFO @ 1590480379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))' 2 test runs
kmac_sideload_invalid 113733907577807502595377442037467560691206349404937271113080686160165217286939 81
UVM_ERROR @ 110159881 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 110159881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_key_error 44626551030521773320125675922682782495996612562672023183124799041180564912322 78
UVM_ERROR @ 70046981 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 70046981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err) 2 test runs
kmac_mubi 58272835292586533413455812785379282318989876294443653959638921772563731400782 84
UVM_INFO @ 219498751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 114478373314409545601347438361852221018403544630237627890395851488260612454584 135
UVM_INFO @ 32746475615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---