Simulation Results: lc_ctrl/volatile_unlock_disabled

 
21/07/2026 19:39:46 DVSim: v1.49.12 sha: b583fba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.73 %
  • code
  • 92.36 %
  • assert
  • 96.83 %
  • func
  • 85.99 %
  • block
  • 96.66 %
  • line
  • 97.35 %
  • branch
  • 91.49 %
  • toggle
  • 85.38 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 58.923us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 57.584us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 48.093us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 90.815us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 36.533us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 35.394us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 48.093us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 36.533us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 221.960us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 210.792us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 29.201us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 226.884us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 5.000s 743.364us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.000s 1718.400us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 5.000s 743.364us 1 1 100.00
lc_ctrl_prog_failure 2.000s 226.884us 1 1 100.00
lc_ctrl_errors 7.000s 1718.400us 1 1 100.00
lc_ctrl_security_escalation 4.000s 168.581us 1 1 100.00
lc_ctrl_jtag_state_failure 24.000s 1379.486us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 316.178us 1 1 100.00
lc_ctrl_jtag_errors 24.000s 16374.546us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 8.000s 1668.203us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.000s 2637.735us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 316.178us 1 1 100.00
lc_ctrl_jtag_errors 24.000s 16374.546us 1 1 100.00
lc_ctrl_jtag_access 3.000s 3142.635us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.000s 4035.778us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 136.712us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 41.744us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 15.000s 983.802us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.000s 473.397us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 28.743us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 940.808us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 71.523us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.000s 585.779us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 16.613us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 141.000s 56112.970us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 80.916us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.000s 20.640us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.000s 20.640us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 57.584us 1 1 100.00
lc_ctrl_csr_rw 1.000s 48.093us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 36.533us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 88.065us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 57.584us 1 1 100.00
lc_ctrl_csr_rw 1.000s 48.093us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 36.533us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 88.065us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 136.621us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 182.716us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 182.716us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 210.792us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 743.364us 1 1 100.00
lc_ctrl_sec_cm 3.000s 136.621us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 743.364us 1 1 100.00
lc_ctrl_sec_cm 3.000s 136.621us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 743.364us 1 1 100.00
lc_ctrl_sec_cm 3.000s 136.621us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 743.364us 1 1 100.00
lc_ctrl_sec_cm 3.000s 136.621us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 743.364us 1 1 100.00
lc_ctrl_sec_cm 3.000s 136.621us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 743.364us 1 1 100.00
lc_ctrl_sec_cm 3.000s 136.621us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 743.364us 1 1 100.00
lc_ctrl_sec_cm 3.000s 136.621us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 5.000s 743.364us 1 1 100.00
lc_ctrl_sec_cm 3.000s 136.621us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.000s 168.581us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 221.960us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.000s 2637.735us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.000s 5577.524us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.000s 5577.524us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 965.839us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 1444.575us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 1444.575us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 19.000s 25106.725us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 45803047605428246272259257384940846464986392220331788382392689101964694511367 2706
UVM_INFO @ 25106725001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---