Simulation Results: lc_ctrl/volatile_unlock_enabled

 
21/07/2026 19:39:46 DVSim: v1.49.12 sha: b583fba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.73 %
  • code
  • 93.39 %
  • assert
  • 96.25 %
  • func
  • 88.54 %
  • block
  • 97.02 %
  • line
  • 97.60 %
  • branch
  • 92.45 %
  • toggle
  • 88.28 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 26.450us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 17.417us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 51.416us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 1941.542us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 319.347us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 39.018us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 51.416us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 319.347us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 137.760us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.000s 1399.680us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 37.333us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 239.946us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.000s 293.536us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.000s 1473.796us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.000s 293.536us 1 1 100.00
lc_ctrl_prog_failure 2.000s 239.946us 1 1 100.00
lc_ctrl_errors 7.000s 1473.796us 1 1 100.00
lc_ctrl_security_escalation 8.000s 269.643us 1 1 100.00
lc_ctrl_jtag_state_failure 14.000s 6462.768us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.000s 164.914us 1 1 100.00
lc_ctrl_jtag_errors 23.000s 13350.722us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.000s 803.661us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.000s 1184.375us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.000s 164.914us 1 1 100.00
lc_ctrl_jtag_errors 23.000s 13350.722us 1 1 100.00
lc_ctrl_jtag_access 7.000s 1035.777us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.000s 1397.621us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 324.232us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 382.110us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 13.000s 4368.546us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 8.000s 707.675us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.000s 59.317us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 151.756us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 115.743us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.000s 549.721us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 14.114us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 105.000s 13043.678us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 27.430us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 189.034us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 189.034us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 17.417us 1 1 100.00
lc_ctrl_csr_rw 2.000s 51.416us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 319.347us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 246.847us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 17.417us 1 1 100.00
lc_ctrl_csr_rw 2.000s 51.416us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 319.347us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 246.847us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 243.665us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 266.310us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 266.310us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.000s 1399.680us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 293.536us 1 1 100.00
lc_ctrl_sec_cm 3.000s 243.665us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 293.536us 1 1 100.00
lc_ctrl_sec_cm 3.000s 243.665us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 293.536us 1 1 100.00
lc_ctrl_sec_cm 3.000s 243.665us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 293.536us 1 1 100.00
lc_ctrl_sec_cm 3.000s 243.665us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 293.536us 1 1 100.00
lc_ctrl_sec_cm 3.000s 243.665us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 293.536us 1 1 100.00
lc_ctrl_sec_cm 3.000s 243.665us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 293.536us 1 1 100.00
lc_ctrl_sec_cm 3.000s 243.665us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.000s 293.536us 1 1 100.00
lc_ctrl_sec_cm 3.000s 243.665us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 8.000s 269.643us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 137.760us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.000s 1184.375us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 4650.274us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 4650.274us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 456.454us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 1039.939us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 1039.939us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 24.000s 4223.255us 1 1 100.00