Simulation Results: mbx

 
21/07/2026 19:39:46 DVSim: v1.49.12 sha: b583fba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.54 %
  • code
  • 91.52 %
  • assert
  • 96.86 %
  • func
  • 77.24 %
  • block
  • 96.88 %
  • line
  • 96.71 %
  • branch
  • 91.89 %
  • toggle
  • 85.96 %
Validation stages
V1
83.33%
V2
81.82%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 57.000s 46373.294us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 39.998us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 27.250us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 3.000s 196.903us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 1.000s 16.472us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 2.000s 4.405us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 27.250us 1 1 100.00
mbx_csr_aliasing 1.000s 16.472us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 1 100.00
mbx_stress 90.000s 10803.391us 1 1 100.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 4.000s 699.836us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 77.000s 4247.292us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 14.000s 2930.618us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 28.110us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 49.131us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 15.885us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 15.885us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 39.998us 1 1 100.00
mbx_csr_rw 1.000s 27.250us 1 1 100.00
mbx_csr_aliasing 1.000s 16.472us 1 1 100.00
mbx_same_csr_outstanding 1.000s 106.815us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 39.998us 1 1 100.00
mbx_csr_rw 1.000s 27.250us 1 1 100.00
mbx_csr_aliasing 1.000s 16.472us 1 1 100.00
mbx_same_csr_outstanding 1.000s 106.815us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 175.965us 1 1 100.00
mbx_sec_cm 1.000s 38.835us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 61101121604779342958748657454412727598699007016540926004091371939818798768965 85
TL item was: req: (cip_tl_seq_item@18595) { a_addr: 'h4a28a8d0 a_data: 'h61145230 a_mask: 'h6 a_size: 'h2 a_param: 'h0 a_source: 'h74 a_opcode: 'h1 a_user: 'h252d4 d_param: 'h0 d_source: 'h74 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 15884555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 67773935072047087867919108685040174662510640257625856298183512636586236804467 86
TL item was: req: (cip_tl_seq_item@17664) { a_addr: 'h45e129f0 a_data: 'h8c1f53b2 a_mask: 'h1 a_size: 'h0 a_param: 'h0 a_source: 'h4f a_opcode: 'h1 a_user: 'h240b8 d_param: 'h0 d_source: 'h4f d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h152a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 4405015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched 1 test run
mbx_stress_zero_delays 83302732910514385728318899532297605110941064632390601791702803520229805364037 320
UVM_INFO @ 699835667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---