Simulation Results: otbn

 
21/07/2026 19:39:46 DVSim: v1.49.12 sha: b583fba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.30 %
  • code
  • 86.08 %
  • assert
  • 90.35 %
  • func
  • 97.46 %
  • block
  • 99.27 %
  • line
  • 99.47 %
  • branch
  • 94.77 %
  • toggle
  • 83.88 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 14.000s 53.617us 1 1 100.00
single_binary 1 1 100.00
otbn_single 10.000s 23.385us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 132.256us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 5.000s 24.958us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 4.000s 105.700us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 44.049us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 5.000s 68.348us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 5.000s 24.958us 1 1 100.00
otbn_csr_aliasing 4.000s 44.049us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 126.000s 13151.477us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 29.000s 1189.827us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 35.000s 366.377us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 56.000s 201.750us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 39.000s 118.031us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 49.000s 373.095us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 9.000s 47.631us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 7.000s 60.872us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 16.000s 104.957us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 6.000s 15.578us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 44.426us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 116.308us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 116.308us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 132.256us 1 1 100.00
otbn_csr_rw 5.000s 24.958us 1 1 100.00
otbn_csr_aliasing 4.000s 44.049us 1 1 100.00
otbn_same_csr_outstanding 6.000s 19.676us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 132.256us 1 1 100.00
otbn_csr_rw 5.000s 24.958us 1 1 100.00
otbn_csr_aliasing 4.000s 44.049us 1 1 100.00
otbn_same_csr_outstanding 6.000s 19.676us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 11.000s 71.570us 1 1 100.00
otbn_dmem_err 9.000s 37.394us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 8.000s 165.361us 0 1 0.00
otbn_controller_ispr_rdata_err 10.000s 223.986us 1 1 100.00
otbn_mac_bignum_acc_err 8.000s 108.030us 1 1 100.00
otbn_urnd_err 5.000s 12.785us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 7.000s 19.238us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 7.000s 13.512us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 22.629us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 332.000s 6044.378us 1 1 100.00
otbn_tl_intg_err 16.000s 103.740us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 25.000s 681.684us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 332.000s 6044.378us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 332.000s 6044.378us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 14.000s 53.617us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 9.000s 37.394us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 11.000s 71.570us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 16.000s 103.740us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 47.631us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 71.570us 1 1 100.00
otbn_dmem_err 9.000s 37.394us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 60.872us 1 1 100.00
otbn_illegal_mem_acc 7.000s 19.238us 1 1 100.00
otbn_sec_cm 332.000s 6044.378us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 332.000s 6044.378us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 10.000s 23.385us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 71.570us 1 1 100.00
otbn_dmem_err 9.000s 37.394us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 60.872us 1 1 100.00
otbn_illegal_mem_acc 7.000s 19.238us 1 1 100.00
otbn_sec_cm 332.000s 6044.378us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 332.000s 6044.378us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 47.631us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 71.570us 1 1 100.00
otbn_dmem_err 9.000s 37.394us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 60.872us 1 1 100.00
otbn_illegal_mem_acc 7.000s 19.238us 1 1 100.00
otbn_sec_cm 332.000s 6044.378us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 332.000s 6044.378us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 10.000s 23.385us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 7.000s 14.258us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 69.202us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 41.000s 329.826us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 41.000s 329.826us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 6.000s 16.549us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 332.000s 6044.378us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 332.000s 6044.378us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 9.000s 65.900us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 332.000s 6044.378us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 332.000s 6044.378us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 11.000s 114.387us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 11.000s 114.387us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 27.426us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 10.000s 23.385us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 10.000s 23.385us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 10.000s 23.385us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 39.000s 118.031us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 10.000s 23.385us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 10.000s 23.385us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 23.000s 151.696us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 10.000s 23.385us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 332.000s 6044.378us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 255.000s 1224.837us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 8.000s 25.182us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
otbn_alu_bignum_mod_err 83301335583552881537050197567669767843302740709822742933644100932528829970310 110
UVM_INFO @ 165361135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 91042135720768482392206669384266861093706661675312497331663183148945810657356 230
UVM_INFO @ 1224836808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---