Simulation Results

Simulation Results: otp_ctrl

21/07/2026 19:39:46 DVSim: v1.49.12 sha: b583fba json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
72.91 %

code
71.28 %

assert
93.71 %

func
53.73 %

line
87.48 %

branch
84.40 %

cond
86.89 %

toggle
61.09 %

FSM
36.56 %

Validation stages

V1		100.00%
V2		60.00%
V2S		66.67%
V3		50.00%

9/9 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
wake_up				1	1	100.00
	otp_ctrl_wake_up	2.100s	837.091us	1	1	100.00
smoke				1	1	100.00
	otp_ctrl_smoke	7.030s	752.916us	1	1	100.00
csr_hw_reset				1	1	100.00
	otp_ctrl_csr_hw_reset	2.460s	83.145us	1	1	100.00
csr_rw				1	1	100.00
	otp_ctrl_csr_rw	1.900s	89.272us	1	1	100.00
csr_bit_bash				1	1	100.00
	otp_ctrl_csr_bit_bash	9.330s	1239.364us	1	1	100.00
csr_aliasing				1	1	100.00
	otp_ctrl_csr_aliasing	6.720s	965.474us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	otp_ctrl_csr_mem_rw_with_rand_reset	1.880s	94.555us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	otp_ctrl_csr_rw	1.900s	89.272us	1	1	100.00
	otp_ctrl_csr_aliasing	6.720s	965.474us	1	1	100.00
mem_walk				1	1	100.00
	otp_ctrl_mem_walk	1.750s	630.824us	1	1	100.00
mem_partial_access				1	1	100.00
	otp_ctrl_mem_partial_access	1.520s	48.344us	1	1	100.00

12/20 passed

60.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
dai_access_partition_walk				0	1	0.00
	otp_ctrl_partition_walk	159.600s	31351.502us	0	1	0.00
init_fail				0	1	0.00
	otp_ctrl_init_fail	2.260s	791.316us	0	1	0.00
partition_check				1	2	50.00
	otp_ctrl_background_chks	5.950s	326.743us	0	1	0.00
	otp_ctrl_check_fail	27.060s	11133.058us	1	1	100.00
regwen_during_otp_init				0	1	0.00
	otp_ctrl_regwen	2.700s	90.346us	0	1	0.00
partition_lock				1	1	100.00
	otp_ctrl_dai_lock	8.030s	1554.071us	1	1	100.00
interface_key_check				1	1	100.00
	otp_ctrl_parallel_key_req	3.530s	164.404us	1	1	100.00
lc_interactions				1	2	50.00
	otp_ctrl_parallel_lc_req	8.400s	1212.740us	0	1	0.00
	otp_ctrl_parallel_lc_esc	8.430s	310.301us	1	1	100.00
otp_dai_errors				1	1	100.00
	otp_ctrl_dai_errs	58.910s	26215.892us	1	1	100.00
otp_macro_errors				0	1	0.00
	otp_ctrl_macro_errs	1.620s	38.549us	0	1	0.00
test_access				0	1	0.00
	otp_ctrl_test_access	10.000s	831.368us	0	1	0.00
stress_all				0	1	0.00
	otp_ctrl_stress_all	30.080s	3206.242us	0	1	0.00
intr_test				1	1	100.00
	otp_ctrl_intr_test	1.960s	168.193us	1	1	100.00
alert_test				1	1	100.00
	otp_ctrl_alert_test	1.940s	874.420us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	otp_ctrl_tl_errors	5.380s	2381.413us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	otp_ctrl_tl_errors	5.380s	2381.413us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	otp_ctrl_csr_hw_reset	2.460s	83.145us	1	1	100.00
	otp_ctrl_csr_rw	1.900s	89.272us	1	1	100.00
	otp_ctrl_csr_aliasing	6.720s	965.474us	1	1	100.00
	otp_ctrl_same_csr_outstanding	2.400s	177.130us	1	1	100.00
tl_d_partial_access				4	4	100.00
	otp_ctrl_csr_hw_reset	2.460s	83.145us	1	1	100.00
	otp_ctrl_csr_rw	1.900s	89.272us	1	1	100.00
	otp_ctrl_csr_aliasing	6.720s	965.474us	1	1	100.00
	otp_ctrl_same_csr_outstanding	2.400s	177.130us	1	1	100.00

V2S

6/9 passed

66.67 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sec_cm_additional_check				1	1	100.00
	otp_ctrl_sec_cm	285.640s	19692.055us	1	1	100.00
tl_intg_err				2	2	100.00
	otp_ctrl_sec_cm	285.640s	19692.055us	1	1	100.00
	otp_ctrl_tl_intg_err	25.170s	1504.748us	1	1	100.00
prim_count_check				1	1	100.00
	otp_ctrl_sec_cm	285.640s	19692.055us	1	1	100.00
prim_fsm_check				1	1	100.00
	otp_ctrl_sec_cm	285.640s	19692.055us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	otp_ctrl_tl_intg_err	25.170s	1504.748us	1	1	100.00
sec_cm_secret_mem_scramble				1	1	100.00
	otp_ctrl_smoke	7.030s	752.916us	1	1	100.00
sec_cm_part_mem_digest				1	1	100.00
	otp_ctrl_smoke	7.030s	752.916us	1	1	100.00
sec_cm_dai_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	285.640s	19692.055us	1	1	100.00
sec_cm_kdi_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	285.640s	19692.055us	1	1	100.00
sec_cm_lci_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	285.640s	19692.055us	1	1	100.00
sec_cm_part_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	285.640s	19692.055us	1	1	100.00
sec_cm_scrmbl_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	285.640s	19692.055us	1	1	100.00
sec_cm_timer_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	285.640s	19692.055us	1	1	100.00
sec_cm_dai_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	285.640s	19692.055us	1	1	100.00
sec_cm_kdi_seed_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	285.640s	19692.055us	1	1	100.00
sec_cm_kdi_entropy_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	285.640s	19692.055us	1	1	100.00
sec_cm_lci_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	285.640s	19692.055us	1	1	100.00
sec_cm_part_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	285.640s	19692.055us	1	1	100.00
sec_cm_scrmbl_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	285.640s	19692.055us	1	1	100.00
sec_cm_timer_integ_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	285.640s	19692.055us	1	1	100.00
sec_cm_timer_cnsty_ctr_redun				1	1	100.00
	otp_ctrl_sec_cm	285.640s	19692.055us	1	1	100.00
sec_cm_timer_lfsr_redun				1	1	100.00
	otp_ctrl_sec_cm	285.640s	19692.055us	1	1	100.00
sec_cm_dai_fsm_local_esc				2	2	100.00
	otp_ctrl_parallel_lc_esc	8.430s	310.301us	1	1	100.00
	otp_ctrl_sec_cm	285.640s	19692.055us	1	1	100.00
sec_cm_lci_fsm_local_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	8.430s	310.301us	1	1	100.00
sec_cm_kdi_fsm_local_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	8.430s	310.301us	1	1	100.00
sec_cm_part_fsm_local_esc				1	2	50.00
	otp_ctrl_parallel_lc_esc	8.430s	310.301us	1	1	100.00
	otp_ctrl_macro_errs	1.620s	38.549us	0	1	0.00
sec_cm_scrmbl_fsm_local_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	8.430s	310.301us	1	1	100.00
sec_cm_timer_fsm_local_esc				2	2	100.00
	otp_ctrl_parallel_lc_esc	8.430s	310.301us	1	1	100.00
	otp_ctrl_sec_cm	285.640s	19692.055us	1	1	100.00
sec_cm_dai_fsm_global_esc				2	2	100.00
	otp_ctrl_parallel_lc_esc	8.430s	310.301us	1	1	100.00
	otp_ctrl_sec_cm	285.640s	19692.055us	1	1	100.00
sec_cm_lci_fsm_global_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	8.430s	310.301us	1	1	100.00
sec_cm_kdi_fsm_global_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	8.430s	310.301us	1	1	100.00
sec_cm_part_fsm_global_esc				1	2	50.00
	otp_ctrl_parallel_lc_esc	8.430s	310.301us	1	1	100.00
	otp_ctrl_macro_errs	1.620s	38.549us	0	1	0.00
sec_cm_scrmbl_fsm_global_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	8.430s	310.301us	1	1	100.00
sec_cm_timer_fsm_global_esc				2	2	100.00
	otp_ctrl_parallel_lc_esc	8.430s	310.301us	1	1	100.00
	otp_ctrl_sec_cm	285.640s	19692.055us	1	1	100.00
sec_cm_part_data_reg_integrity				0	1	0.00
	otp_ctrl_init_fail	2.260s	791.316us	0	1	0.00
sec_cm_part_data_reg_bkgn_chk				1	1	100.00
	otp_ctrl_check_fail	27.060s	11133.058us	1	1	100.00
sec_cm_part_mem_regren				1	1	100.00
	otp_ctrl_dai_lock	8.030s	1554.071us	1	1	100.00
sec_cm_part_mem_sw_unreadable				1	1	100.00
	otp_ctrl_dai_lock	8.030s	1554.071us	1	1	100.00
sec_cm_part_mem_sw_unwritable				1	1	100.00
	otp_ctrl_dai_lock	8.030s	1554.071us	1	1	100.00
sec_cm_lc_part_mem_sw_noaccess				1	1	100.00
	otp_ctrl_dai_lock	8.030s	1554.071us	1	1	100.00
sec_cm_access_ctrl_mubi				1	1	100.00
	otp_ctrl_dai_lock	8.030s	1554.071us	1	1	100.00
sec_cm_token_valid_ctrl_mubi				1	1	100.00
	otp_ctrl_smoke	7.030s	752.916us	1	1	100.00
sec_cm_lc_ctrl_intersig_mubi				1	1	100.00
	otp_ctrl_dai_lock	8.030s	1554.071us	1	1	100.00
sec_cm_test_bus_lc_gated				1	1	100.00
	otp_ctrl_smoke	7.030s	752.916us	1	1	100.00
sec_cm_test_tl_lc_gate_fsm_sparse				1	1	100.00
	otp_ctrl_sec_cm	285.640s	19692.055us	1	1	100.00
sec_cm_direct_access_config_regwen				0	1	0.00
	otp_ctrl_regwen	2.700s	90.346us	0	1	0.00
sec_cm_check_trigger_config_regwen				1	1	100.00
	otp_ctrl_smoke	7.030s	752.916us	1	1	100.00
sec_cm_check_config_regwen				1	1	100.00
	otp_ctrl_smoke	7.030s	752.916us	1	1	100.00
sec_cm_macro_mem_integrity				0	1	0.00
	otp_ctrl_macro_errs	1.620s	38.549us	0	1	0.00

1/2 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
otp_ctrl_low_freq_read				0	1	0.00
	otp_ctrl_low_freq_read	91.220s	62797.543us	0	1	0.00
stress_all_with_rand_reset				1	1	100.00
	otp_ctrl_stress_all_with_rand_reset	60.720s	20338.406us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value:				2 test runs
	otp_ctrl_init_fail	54755928475287757200784002773787656159539461202317587065089328108185869799473	765	UVM_INFO @ 791315525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	80029781634567858260284894743976753047738531201191375521215205693602591316102	1472	UVM_INFO @ 90345658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [] vs []) dai addr ed* rdata* readout mismatch				1 test run
	otp_ctrl_partition_walk	5286808686257621329539022182609588438286428263890737129098456926466243315712	110201	UVM_INFO @ 31351502361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [] vs []) dai addr ed* rdata* readout mismatch				1 test run
	otp_ctrl_low_freq_read	62519180903183819583948086431886169134283823025926637476912327689544005287288	89	UVM_INFO @ 62797542772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs []) reg name: otp_ctrl_core_reg_block.err_code_				1 test run
	otp_ctrl_background_chks	27713587569033885676610378081320149771333926663032966021696348070583906518478	3264	UVM_INFO @ 326743205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:964) [scoreboard] Check failed (csr.get_mirrored_value() \| status_mask) == (item.d_data \| status_mask) (* [] vs []) reg name: status, compare_mask				1 test run
	otp_ctrl_parallel_lc_req	55303199565992697434226178228011917604770226491382956699093673101628821687236	7376	UVM_INFO @ 1212739817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs []) reg name: otp_ctrl_core_reg_block.direct_access_rdata_				1 test run
	otp_ctrl_macro_errs	6339933574496466608852569129366845012853906182601508066280425233618488843053	158	UVM_INFO @ 38548743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:677) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [] vs [*]) Interrupt_pin: OtpErr				1 test run
	otp_ctrl_test_access	68593133172548841250460634764773548879541143071154324461363363451611362665214	10644	UVM_INFO @ 831367872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: otp_ctrl_core_reg_block.intr_state				1 test run
	otp_ctrl_stress_all	15993627239274352478281598033497847702053328303522795028456959508463003713505	45779	UVM_INFO @ 3206242201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---