Simulation Results: rstmgr

 
21/07/2026 19:39:46 DVSim: v1.49.12 sha: b583fba json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.05 %
  • code
  • 99.12 %
  • assert
  • 98.35 %
  • func
  • 96.69 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 97.95 %
  • toggle
  • 99.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.170s 73.138us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.700s 95.244us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.880s 37.573us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.410s 82.725us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.420s 39.927us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.050s 68.218us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.880s 37.573us 1 1 100.00
rstmgr_csr_aliasing 1.420s 39.927us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.560s 100.712us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.190s 39.037us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.980s 75.608us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.670s 586.531us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.670s 586.531us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.670s 586.531us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.670s 586.531us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 10.910s 1666.806us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.200s 38.607us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.680s 53.968us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.680s 53.968us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.700s 95.244us 1 1 100.00
rstmgr_csr_rw 0.880s 37.573us 1 1 100.00
rstmgr_csr_aliasing 1.420s 39.927us 1 1 100.00
rstmgr_same_csr_outstanding 1.120s 37.017us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.700s 95.244us 1 1 100.00
rstmgr_csr_rw 0.880s 37.573us 1 1 100.00
rstmgr_csr_aliasing 1.420s 39.927us 1 1 100.00
rstmgr_same_csr_outstanding 1.120s 37.017us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 16.430s 3469.581us 1 1 100.00
rstmgr_tl_intg_err 3.850s 342.183us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 16.430s 3469.581us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 16.430s 3469.581us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 3.850s 342.183us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.320s 55.595us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.940s 483.468us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.390s 291.585us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 16.430s 3469.581us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.880s 37.573us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.880s 37.573us 1 1 100.00