Simulation Results: rv_dm/use_dmi_interface

 
21/07/2026 19:39:46 DVSim: v1.49.12 sha: b583fba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.44 %
  • code
  • 73.84 %
  • assert
  • 96.51 %
  • func
  • 91.96 %
  • block
  • 89.69 %
  • line
  • 89.42 %
  • branch
  • 72.02 %
  • toggle
  • 71.40 %
  • FSM
  • 62.50 %
Validation stages
V1
96.30%
V2
69.57%
V2S
85.71%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 35.000s 2597.709us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 31.000s 205.318us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 30.000s 401.386us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 34.000s 16478.963us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 31.000s 731.179us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 34.000s 1430.719us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 32.000s 3025.386us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 32.000s 64.915us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 42.000s 25080.441us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 31.000s 576.700us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 31.000s 388.713us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 31.000s 353.934us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 30.000s 97.775us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 31.000s 170.144us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 31.000s 902.752us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 31.000s 282.163us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 31.000s 633.555us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 31.000s 576.700us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 31.000s 342.538us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 31.000s 601.573us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 31.000s 353.934us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 32.000s 123.293us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 31.000s 122.325us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 32.000s 493.028us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 74.000s 90848.885us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 45.000s 1920.600us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_dm_csr_mem_rw_with_rand_reset 31.000s 148.258us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 45.000s 1920.600us 1 1 100.00
rv_dm_csr_rw 32.000s 493.028us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 30.000s 109.070us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 32.000s 58.176us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 35.000s 2597.709us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 31.000s 799.838us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 32.000s 251.268us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 30.000s 164.687us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 35.000s 2562.258us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 30.000s 1041.902us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 32.000s 70.262us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 46.000s 6255.736us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 32.000s 4686.916us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 30.000s 95.485us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 30.000s 684.899us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 35.000s 235.823us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 31.000s 239.324us 0 1 0.00
tap_ctrl_transitions 2 2 100.00
rv_dm_tap_fsm 47.000s 10169.234us 1 1 100.00
rv_dm_tap_fsm_rand_reset 69.000s 12335.134us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 30.000s 457.915us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 29.000s 491.999us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 30.000s 61.466us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_dm_tl_errors 30.000s 252.998us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_dm_tl_errors 30.000s 252.998us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 45.000s 1920.600us 1 1 100.00
rv_dm_csr_hw_reset 31.000s 122.325us 1 1 100.00
rv_dm_csr_rw 32.000s 493.028us 1 1 100.00
rv_dm_same_csr_outstanding 32.000s 294.836us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 45.000s 1920.600us 1 1 100.00
rv_dm_csr_hw_reset 31.000s 122.325us 1 1 100.00
rv_dm_csr_rw 32.000s 493.028us 1 1 100.00
rv_dm_same_csr_outstanding 32.000s 294.836us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_sec_cm 34.000s 1923.844us 1 1 100.00
rv_dm_tl_intg_err 41.000s 4982.507us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 41.000s 4982.507us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 30.000s 684.899us 1 1 100.00
rv_dm_debug_disabled 29.000s 37.338us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 30.000s 684.899us 1 1 100.00
rv_dm_debug_disabled 29.000s 37.338us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 35.000s 2597.709us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 31.000s 284.542us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 0 1 0.00
rv_dm_sparse_lc_gate_fsm 29.000s 75.889us 0 1 0.00
sec_cm_mem_tl_lc_gate_fsm_sparse 0 1 0.00
rv_dm_sparse_lc_gate_fsm 29.000s 75.889us 0 1 0.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 31.000s 284.542us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 39.000s 2036.152us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 130.000s 300000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared: 3 test runs
rv_dm_sba_tl_access 61665766668920431129272248408975310249324831771179390513642826783419230263175 87
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23818
rv_dm_bad_sba_tl_access 62141555027888808704452350058746492981845250599235047606163194418725915239618 99
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23817
rv_dm_autoincr_sba_tl_access 10049191614643611871301793413637612624546923172608578653942565186512185450368 147
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23943
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == *'b* (* [*] vs * [*]) 2 test runs
rv_dm_mem_tl_access_resuming 108410210076806993912007967889215114075448127797191205207031165544884362905484 87
UVM_INFO @ 97775002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 25224130579054459022839793912817329085615544776963596514707519431322480237210 88
UVM_INFO @ 491998908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [*] vs * [*]) 2 test runs
rv_dm_hart_unavail 64821265656280023529646294113440473718717496269114784651385845343671276388846 87
UVM_INFO @ 239324494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 76497194671056086716208665691257569756239989453501090208391854226685123669221 122
UVM_INFO @ 2036152093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp 1 test run
rv_dm_delayed_resp_sba_tl_access 113073432520785935844068980758182787072576055408710522916090033873891028202664 107
UVM_INFO @ 70262066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) 1 test run
rv_dm_jtag_dmi_debug_disabled 84438771774047278587661196487319999632697612076564772670720227075479661650107 87
UVM_INFO @ 95484580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error 1 test run
rv_dm_sparse_lc_gate_fsm 20498231319663997963862754572191796526928992630587297839638753821928070352613 87
UVM_INFO @ 75889409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
rv_dm_scanmode 77338861597542158298145684371461621449962894367054020190794333306384228486229 87
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---