Simulation Results: rv_timer

 
21/07/2026 19:39:46 DVSim: v1.49.12 sha: b583fba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.94 %
  • code
  • 90.45 %
  • assert
  • 97.78 %
  • func
  • 99.58 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.000s 46.875us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 99.034us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 12.657us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.000s 276.683us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 2.000s 70.215us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 193.433us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 12.657us 1 1 100.00
rv_timer_csr_aliasing 2.000s 70.215us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 2.000s 275.458us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 1208.423us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 1.000s 91.188us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 1.000s 91.188us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.000s 1570.119us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 27.367us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 16.313us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 1272.552us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 1272.552us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 99.034us 1 1 100.00
rv_timer_csr_rw 1.000s 12.657us 1 1 100.00
rv_timer_csr_aliasing 2.000s 70.215us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 20.088us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 99.034us 1 1 100.00
rv_timer_csr_rw 1.000s 12.657us 1 1 100.00
rv_timer_csr_aliasing 2.000s 70.215us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 20.088us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 264.242us 1 1 100.00
rv_timer_tl_intg_err 1.000s 91.552us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.000s 91.552us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.000s 117.729us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.000s 52.757us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 34.000s 6731.980us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 70339134907445188123985324387402334423108784972038036954302227189087291388811 84
UVM_INFO @ 117729270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 69894538701693408991536279696541171854993276909925488114095763870876899166371 84
UVM_INFO @ 275458356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 67397933140777975881658507898858761253115091511105993453432292084169348446588 85
UVM_INFO @ 52756968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---