Simulation Results: spi_host

 
21/07/2026 19:39:46 DVSim: v1.49.12 sha: b583fba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.26 %
  • code
  • 90.65 %
  • assert
  • 94.90 %
  • func
  • 88.24 %
  • block
  • 96.56 %
  • line
  • 98.27 %
  • branch
  • 92.45 %
  • toggle
  • 71.87 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 13.000s 1396.573us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 19.683us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 17.172us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 351.478us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 31.406us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 37.975us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 17.172us 1 1 100.00
spi_host_csr_aliasing 2.000s 31.406us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 16.205us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 50.622us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 52.937us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 218.798us 1 1 100.00
spi_host_error_cmd 2.000s 141.693us 1 1 100.00
spi_host_event 7.000s 740.594us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 3.000s 303.714us 1 1 100.00
speed 1 1 100.00
spi_host_speed 3.000s 303.714us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 3.000s 303.714us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 126.000s 14955.030us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 3.000s 586.676us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 51.397us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 3.000s 303.714us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 3.000s 303.714us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 13.000s 1396.573us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 13.000s 1396.573us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 18.000s 970.029us 1 1 100.00
spien 1 1 100.00
spi_host_spien 12.000s 2955.350us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 1077.000s 659330.643us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 116.689us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 218.798us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 20.055us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 16.837us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 484.776us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 484.776us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 19.683us 1 1 100.00
spi_host_csr_rw 1.000s 17.172us 1 1 100.00
spi_host_csr_aliasing 2.000s 31.406us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 27.697us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 19.683us 1 1 100.00
spi_host_csr_rw 1.000s 17.172us 1 1 100.00
spi_host_csr_aliasing 2.000s 31.406us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 27.697us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 85.465us 1 1 100.00
spi_host_sec_cm 1.000s 118.070us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 85.465us 1 1 100.00