Simulation Results: sram_ctrl/main

 
21/07/2026 19:39:46 DVSim: v1.49.12 sha: b583fba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.19 %
  • code
  • 95.69 %
  • assert
  • 98.10 %
  • func
  • 94.77 %
  • block
  • 96.03 %
  • line
  • 96.75 %
  • branch
  • 94.17 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 718.608us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 15.721us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 37.522us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 188.897us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 14.025us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 352.495us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 37.522us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 14.025us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 93.000s 12313.912us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 97.000s 5779.465us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 39.000s 61644.617us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 116.000s 3989.603us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 177.000s 70007.402us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 53.000s 13985.530us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 17.000s 10628.130us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 20.000s 5117.529us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 1359.009us 1 1 100.00
sram_ctrl_partial_access_b2b 131.000s 48213.984us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 5.000s 1415.896us 0 1 0.00
sram_ctrl_throughput_w_partial_write 6.000s 673.754us 0 1 0.00
sram_ctrl_throughput_w_readback 4.000s 2655.295us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 12.000s 4865.720us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 684.779us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 88.000s 50888.186us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 15.069us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 137.279us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 137.279us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 15.721us 1 1 100.00
sram_ctrl_csr_rw 1.000s 37.522us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 14.025us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 47.033us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 15.721us 1 1 100.00
sram_ctrl_csr_rw 1.000s 37.522us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 14.025us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 47.033us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 19.000s 7256.515us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 537.933us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 256.199us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 537.933us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 256.199us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 4865.720us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 4865.720us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 37.522us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 20.000s 5117.529us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 20.000s 5117.529us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 20.000s 5117.529us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 17.000s 10628.130us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 669.732us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 19.000s 7256.515us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.000s 2955.002us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 718.608us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 718.608us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 20.000s 5117.529us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 537.933us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 17.000s 10628.130us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 537.933us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 537.933us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 718.608us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 537.933us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 11.000s 458.212us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 94196993372651548115536929148037688874582346959477789193445514270949317819604 86
UVM_INFO @ 1415896003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 97147075007633981307375337252117152828169253549433994238702256726088205360063 86
UVM_INFO @ 673753764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 56630977035963946356730296935156810351276505353349074675351167432447475778402 86
UVM_INFO @ 2655294991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---