Simulation Results: sram_ctrl/ret

 
21/07/2026 19:39:46 DVSim: v1.49.12 sha: b583fba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.00 %
  • code
  • 83.34 %
  • assert
  • 97.26 %
  • func
  • 95.40 %
  • block
  • 93.76 %
  • line
  • 94.91 %
  • branch
  • 89.51 %
  • toggle
  • 82.29 %
  • FSM
  • 66.67 %
Validation stages
V1
87.50%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 220.248us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 15.297us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.416us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 211.146us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 73.321us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 10013.977us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 11.416us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 73.321us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 6.000s 205.437us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 125.220us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 14.000s 7416.415us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 107.000s 2792.192us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 6.000s 1351.654us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 19.000s 794.992us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 3.000s 224.927us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 13.000s 4687.671us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 58.589us 1 1 100.00
sram_ctrl_partial_access_b2b 202.000s 16527.474us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 1.000s 42.911us 0 1 0.00
sram_ctrl_throughput_w_partial_write 1.000s 148.056us 0 1 0.00
sram_ctrl_throughput_w_readback 1.000s 112.250us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 4.000s 333.436us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 27.662us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 28.000s 8266.929us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 33.704us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 293.167us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 293.167us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 15.297us 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.416us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 73.321us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 93.848us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 15.297us 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.416us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 73.321us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 93.848us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 1160.965us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.000s 1115.546us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1096.282us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.000s 1115.546us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1096.282us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 4.000s 333.436us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 4.000s 333.436us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.416us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 13.000s 4687.671us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 13.000s 4687.671us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 13.000s 4687.671us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 3.000s 224.927us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 67.957us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 1160.965us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 41.688us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 220.248us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 220.248us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 13.000s 4687.671us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.000s 1115.546us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 3.000s 224.927us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.000s 1115.546us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 1115.546us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 220.248us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 1115.546us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 51.000s 3348.482us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 9949814434042272751071593433950079140347181605545111588765954768135989878323 86
UVM_INFO @ 42911105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 25997482647373698997473061352589424969440786788294700423597194261882539134805 86
UVM_INFO @ 148055908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 80458077595864690614210609537052133574481560248810104411424438821798201396383 86
UVM_INFO @ 112250438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (sram_ctrl_base_vseq.sv:168) [sram_ctrl_common_vseq] Timed out waiting for initialization done 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 62678197035939542742867958752367630870497875987756715999036077035230160753802 85
UVM_INFO @ 10013976775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---