Simulation Results: ac_range_check

 
22/07/2026 19:39:31 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.08 %
  • code
  • 93.29 %
  • assert
  • 97.75 %
  • func
  • 58.21 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 81.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 27.000s 3000.618us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 28.000s 718.234us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 177.161us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 51.853us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 35.000s 3088.167us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 19.000s 5439.880us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 51.431us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 51.853us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 5439.880us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 71.322us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 28.000s 6284.121us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 85.000s 2021.677us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 14.072us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 1.000s 13.310us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 79.105us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 79.105us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 177.161us 1 1 100.00
ac_range_check_csr_rw 2.000s 51.853us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 5439.880us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 887.382us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 177.161us 1 1 100.00
ac_range_check_csr_rw 2.000s 51.853us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 5439.880us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 887.382us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 2824.674us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 2824.674us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 2824.674us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 2824.674us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 81.000s 5010.842us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 36.321us 1 1 100.00
ac_range_check_tl_intg_err 6.000s 150.078us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 229.000s 13982.692us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 29.000s 9742.332us 1 1 100.00