Simulation Results: aes/gcm_masked

 
22/07/2026 19:39:31 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.75 %
  • code
  • 95.45 %
  • assert
  • 98.29 %
  • func
  • 66.51 %
  • block
  • 96.13 %
  • line
  • 97.82 %
  • branch
  • 90.45 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
94.74%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 71.845us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 239.463us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 70.668us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 66.249us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 230.833us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 230.482us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 172.466us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 66.249us 1 1 100.00
aes_csr_aliasing 2.000s 230.482us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 239.463us 1 1 100.00
aes_config_error 3.000s 245.549us 1 1 100.00
aes_stress 11.000s 843.650us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 239.463us 1 1 100.00
aes_config_error 3.000s 245.549us 1 1 100.00
aes_stress 11.000s 843.650us 1 1 100.00
back2back 2 2 100.00
aes_stress 11.000s 843.650us 1 1 100.00
aes_b2b 9.000s 1602.584us 1 1 100.00
backpressure 1 1 100.00
aes_stress 11.000s 843.650us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 239.463us 1 1 100.00
aes_config_error 3.000s 245.549us 1 1 100.00
aes_stress 11.000s 843.650us 1 1 100.00
aes_alert_reset 9.000s 3846.019us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 57.421us 1 1 100.00
aes_config_error 3.000s 245.549us 1 1 100.00
aes_alert_reset 9.000s 3846.019us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 6.000s 202.852us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 704.907us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 7.000s 208.208us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 9.000s 3846.019us 1 1 100.00
stress 1 1 100.00
aes_stress 11.000s 843.650us 1 1 100.00
sideload 2 2 100.00
aes_stress 11.000s 843.650us 1 1 100.00
aes_sideload 3.000s 264.404us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 254.114us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 3.000s 382.213us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 84.359us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 57.033us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 1.000s 66.278us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 1.000s 66.278us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 70.668us 1 1 100.00
aes_csr_rw 2.000s 66.249us 1 1 100.00
aes_csr_aliasing 2.000s 230.482us 1 1 100.00
aes_same_csr_outstanding 1.000s 86.654us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 70.668us 1 1 100.00
aes_csr_rw 2.000s 66.249us 1 1 100.00
aes_csr_aliasing 2.000s 230.482us 1 1 100.00
aes_same_csr_outstanding 1.000s 86.654us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 4.000s 151.923us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 250.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 66.678us 1 1 100.00
aes_cipher_fi 2.000s 84.370us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 117.206us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 117.206us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 117.206us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 117.206us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 325.229us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 8.000s 1282.670us 1 1 100.00
aes_tl_intg_err 3.000s 388.674us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 388.674us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 9.000s 3846.019us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 117.206us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 117.206us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 239.463us 1 1 100.00
aes_stress 11.000s 843.650us 1 1 100.00
aes_alert_reset 9.000s 3846.019us 1 1 100.00
aes_core_fi 2.000s 111.031us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 84.359us 1 1 100.00
aes_config_error 3.000s 245.549us 1 1 100.00
aes_stress 11.000s 843.650us 1 1 100.00
aes_core_fi 2.000s 111.031us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 117.206us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 89.493us 1 1 100.00
aes_stress 11.000s 843.650us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 11.000s 843.650us 1 1 100.00
aes_sideload 3.000s 264.404us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 89.493us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 89.493us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 89.493us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 89.493us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 89.493us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 11.000s 843.650us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 11.000s 843.650us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 250.000s 200000.000us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 250.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 66.678us 1 1 100.00
aes_cipher_fi 2.000s 84.370us 1 1 100.00
aes_ctr_fi 3.000s 74.185us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 250.000s 200000.000us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 250.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 66.678us 1 1 100.00
aes_cipher_fi 2.000s 84.370us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 84.370us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 250.000s 200000.000us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 250.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 66.678us 1 1 100.00
aes_ctr_fi 3.000s 74.185us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 250.000s 200000.000us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 250.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 66.678us 1 1 100.00
aes_cipher_fi 2.000s 84.370us 1 1 100.00
aes_ctr_fi 3.000s 74.185us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 9.000s 3846.019us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 250.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 66.678us 1 1 100.00
aes_cipher_fi 2.000s 84.370us 1 1 100.00
aes_ctr_fi 3.000s 74.185us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 250.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 66.678us 1 1 100.00
aes_cipher_fi 2.000s 84.370us 1 1 100.00
aes_ctr_fi 3.000s 74.185us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 250.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 66.678us 1 1 100.00
aes_ctr_fi 3.000s 74.185us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 1.000s 67.219us 1 1 100.00
aes_fi 250.000s 200000.000us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 250.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 66.678us 1 1 100.00
aes_cipher_fi 2.000s 84.370us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 13.000s 631.420us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_reseed 13926172029171326269858529545482897220134431197811861557948856125113435521355 11601
UVM_INFO @ 151923081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 10816806480152046245134344512641898628658287816375551048625258354693916088505 3225
UVM_INFO @ 382212633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
aes_fi 39147441148848420525912444450070988248908557877963426088435421642432644766894 410655
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:1082) virtual_sequencer [aes_reseed_vseq] 1 test run
aes_stress_all_with_rand_reset 60473712145574599976481034963035346987141373697257583773249989771467094847720 427
Was able to clear FATAL ALERT without reset
---| Idle: 0
---| Stall: 0