Simulation Results: alert_handler

 
22/07/2026 19:39:31 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.95 %
  • code
  • 91.71 %
  • assert
  • 98.38 %
  • func
  • 76.75 %
  • line
  • 99.73 %
  • branch
  • 98.64 %
  • cond
  • 92.68 %
  • toggle
  • 90.06 %
  • FSM
  • 77.42 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 30.080s 988.324us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 4.640s 255.192us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 4.060s 72.925us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 117.390s 13824.477us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 117.010s 2275.999us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 3.710s 657.510us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 4.060s 72.925us 1 1 100.00
alert_handler_csr_aliasing 117.010s 2275.999us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 148.510s 18006.004us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 36.710s 3673.170us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 2539.880s 67775.325us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 24.160s 346.103us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 30.080s 988.324us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 33.080s 544.895us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 12.080s 172.929us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 32.920s 6293.719us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 1859.340s 49116.426us 1 1 100.00
alert_handler_lpg_stub_clk 1776.930s 48617.607us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 131.470s 14546.352us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 4.470s 84.468us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 3.110s 109.814us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.380s 16.003us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 23.960s 4831.372us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 23.960s 4831.372us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 4.640s 255.192us 1 1 100.00
alert_handler_csr_rw 4.060s 72.925us 1 1 100.00
alert_handler_csr_aliasing 117.010s 2275.999us 1 1 100.00
alert_handler_same_csr_outstanding 21.410s 843.180us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 4.640s 255.192us 1 1 100.00
alert_handler_csr_rw 4.060s 72.925us 1 1 100.00
alert_handler_csr_aliasing 117.010s 2275.999us 1 1 100.00
alert_handler_same_csr_outstanding 21.410s 843.180us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 137.030s 7576.317us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 137.030s 7576.317us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 137.030s 7576.317us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 137.030s 7576.317us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 976.330s 137872.975us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 19.480s 632.810us 1 1 100.00
alert_handler_tl_intg_err 3.270s 208.553us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 3.270s 208.553us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 137.030s 7576.317us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 30.080s 988.324us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 30.080s 988.324us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 30.080s 988.324us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 30.080s 988.324us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 24.160s 346.103us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1859.340s 49116.426us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 24.160s 346.103us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2539.880s 67775.325us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2539.880s 67775.325us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 19.480s 632.810us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 19.480s 632.810us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 19.480s 632.810us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 19.480s 632.810us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 19.480s 632.810us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 19.480s 632.810us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 19.480s 632.810us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 19.480s 632.810us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 19.480s 632.810us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 33.320s 9997.548us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 64019338049623951336301126888391065496188902099535942674003887879826524226723 88
UVM_INFO @ 6293718708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 85320072329584446025193781623798649403755376611328077885407174943503544145544 92
UVM_INFO @ 84467771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 95585004488326870015584266714909771947746385629017691359798413917764983149563 103
UVM_INFO @ 9997547978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---