Simulation Results: clkmgr

 
22/07/2026 19:39:31 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.21 %
  • code
  • 78.52 %
  • assert
  • 92.98 %
  • func
  • 66.12 %
  • line
  • 90.73 %
  • branch
  • 92.98 %
  • cond
  • 85.21 %
  • toggle
  • 98.68 %
  • FSM
  • 25.00 %
Validation stages
V1
50.00%
V2
76.92%
V2S
50.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.990s 41.084us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.880s 15.290us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.830s 15.263us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 1.810s 134.142us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.820s 6.147us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.640s 3.860us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.830s 15.263us 1 1 100.00
clkmgr_csr_aliasing 0.820s 6.147us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.790s 13.198us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.020s 50.213us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.970s 36.146us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.990s 41.084us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 1.000s 30.490us 1 1 100.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.700s 9.250us 0 1 0.00
frequency_overflow 1 1 100.00
clkmgr_frequency 1.000s 30.490us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 1.650s 109.337us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.970s 15.584us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 9.140s 852.416us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 9.140s 852.416us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 0.880s 15.290us 1 1 100.00
clkmgr_csr_rw 0.830s 15.263us 1 1 100.00
clkmgr_csr_aliasing 0.820s 6.147us 0 1 0.00
clkmgr_same_csr_outstanding 0.590s 2.398us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 0.880s 15.290us 1 1 100.00
clkmgr_csr_rw 0.830s 15.263us 1 1 100.00
clkmgr_csr_aliasing 0.820s 6.147us 0 1 0.00
clkmgr_same_csr_outstanding 0.590s 2.398us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 89.100s 10362.474us 0 1 0.00
clkmgr_tl_intg_err 0.680s 5.877us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.260s 73.075us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.260s 73.075us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.260s 73.075us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.260s 73.075us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.720s 4.316us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.680s 5.877us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 1.000s 30.490us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.700s 9.250us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.260s 73.075us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.640s 109.621us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.830s 15.263us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 89.100s 10362.474us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.830s 15.263us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.830s 15.263us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 89.100s 10362.474us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.890s 13.233us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.500s 18.066us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 3 test runs
clkmgr_shadow_reg_errors_with_csr_rw 3070521792184799239580669938394732306227223404003099658230714841285406723604 75
UVM_INFO @ 4316272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 60463666259283210624314779120645614915036072841103738383869857103397444008735 75
UVM_INFO @ 6146508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 29903704248891260169089161061400305688099175944180926839228984614177351355541 76
UVM_INFO @ 3860115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 96830926742738018520054831226369927174551972794034329652238757615085958727453 77
UVM_INFO @ 9250091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 63055643130999546356412220958518379321998397421118007420302350055244878119606 85
UVM_INFO @ 18066293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.main_meas_ctrl_en 1 test run
clkmgr_regwen 6583919017011769755804670899834461785160185428982274506577644785606998745030 74
UVM_INFO @ 13233178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 45327601582559426646262418323661763154426417278490244724966688621025169911054 144
UVM_INFO @ 10362473629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 1 test run
clkmgr_tl_intg_err 7982255497922611549759008686758130124178195033938065243753364882964297081587 82
UVM_INFO @ 5876528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 12926590742276737664858708848078491715225540046994656881317079343170906585334 75
UVM_INFO @ 134141939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 41239941058952537638507120182611074948910789517187568613109087675150843162433 75
UVM_INFO @ 2397592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---