Simulation Results: edn/edn0

 
22/07/2026 19:39:31 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 77.10 %
  • code
  • 86.11 %
  • assert
  • 96.24 %
  • func
  • 48.95 %
  • block
  • 94.29 %
  • line
  • 97.12 %
  • branch
  • 87.72 %
  • toggle
  • 75.88 %
  • FSM
  • 83.72 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 46.226us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 20.162us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 26.908us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.000s 168.616us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 32.127us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.000s 65.165us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 26.908us 1 1 100.00
edn_csr_aliasing 2.000s 32.127us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.000s 69.066us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.000s 69.066us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.000s 69.066us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 41.490us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 309.773us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 20.738us 1 1 100.00
disable 2 2 100.00
edn_disable 1.000s 37.781us 1 1 100.00
edn_disable_auto_req_mode 2.000s 250.901us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.000s 130.255us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 2.000s 57.276us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 33.099us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.000s 114.595us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.000s 114.595us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 20.162us 1 1 100.00
edn_csr_rw 2.000s 26.908us 1 1 100.00
edn_csr_aliasing 2.000s 32.127us 1 1 100.00
edn_same_csr_outstanding 2.000s 16.930us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 20.162us 1 1 100.00
edn_csr_rw 2.000s 26.908us 1 1 100.00
edn_csr_aliasing 2.000s 32.127us 1 1 100.00
edn_same_csr_outstanding 2.000s 16.930us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.000s 557.427us 1 1 100.00
edn_tl_intg_err 3.000s 1243.138us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 32.216us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 309.773us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.000s 557.427us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.000s 557.427us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.000s 557.427us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.000s 557.427us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 309.773us 1 1 100.00
edn_sec_cm 7.000s 557.427us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 309.773us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.000s 1243.138us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 28.000s 3715.825us 1 1 100.00