Simulation Results: edn/edn1

 
22/07/2026 19:39:31 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.10 %
  • code
  • 81.13 %
  • assert
  • 97.14 %
  • func
  • 80.04 %
  • line
  • 97.80 %
  • branch
  • 92.64 %
  • cond
  • 87.54 %
  • toggle
  • 86.78 %
  • FSM
  • 40.91 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.800s 29.815us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.860s 60.091us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.000s 22.929us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.460s 539.363us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.240s 65.349us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.130s 29.023us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.000s 22.929us 1 1 100.00
edn_csr_aliasing 1.240s 65.349us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.100s 60.165us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.100s 60.165us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.100s 60.165us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.830s 23.783us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.110s 46.494us 1 1 100.00
errs 1 1 100.00
edn_err 1.070s 51.004us 1 1 100.00
disable 1 2 50.00
edn_disable 0.810s 13.678us 1 1 100.00
edn_disable_auto_req_mode 2.290s 500.000us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 3.170s 388.139us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.820s 12.801us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.780s 13.612us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.720s 592.675us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.720s 592.675us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.860s 60.091us 1 1 100.00
edn_csr_rw 1.000s 22.929us 1 1 100.00
edn_csr_aliasing 1.240s 65.349us 1 1 100.00
edn_same_csr_outstanding 0.930s 16.050us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.860s 60.091us 1 1 100.00
edn_csr_rw 1.000s 22.929us 1 1 100.00
edn_csr_aliasing 1.240s 65.349us 1 1 100.00
edn_same_csr_outstanding 0.930s 16.050us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.380s 149.087us 1 1 100.00
edn_tl_intg_err 2.670s 217.348us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.780s 54.067us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.110s 46.494us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.380s 149.087us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.380s 149.087us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.380s 149.087us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.380s 149.087us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.110s 46.494us 1 1 100.00
edn_sec_cm 2.380s 149.087us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.110s 46.494us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.670s 217.348us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 20.590s 2745.938us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
edn_disable_auto_req_mode 96615535273495845324049066965822482213941736163392736260493368750106751935687 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---