| V1 |
|
83.33% |
| V2 |
|
87.50% |
| V2S |
|
71.43% |
| V3 |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| entropy_src_smoke | 2.000s | 25.027us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| entropy_src_csr_hw_reset | 3.000s | 140.628us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| entropy_src_csr_rw | 2.000s | 27.127us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| entropy_src_csr_bit_bash | 15.000s | 3823.012us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| entropy_src_csr_aliasing | 3.000s | 141.379us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| entropy_src_csr_mem_rw_with_rand_reset | 2.000s | 30.815us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| entropy_src_csr_rw | 2.000s | 27.127us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 3.000s | 141.379us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 1 | 3 | 33.33 | |||
| entropy_src_smoke | 2.000s | 25.027us | 1 | 1 | 100.00 | |
| entropy_src_rng | 136.000s | 6275.917us | 0 | 1 | 0.00 | |
| entropy_src_fw_ov | 70.000s | 5309.942us | 0 | 1 | 0.00 | |
| firmware_mode | 0 | 1 | 0.00 | |||
| entropy_src_fw_ov | 70.000s | 5309.942us | 0 | 1 | 0.00 | |
| rng_mode | 0 | 1 | 0.00 | |||
| entropy_src_rng | 136.000s | 6275.917us | 0 | 1 | 0.00 | |
| rng_max_rate | 1 | 1 | 100.00 | |||
| entropy_src_rng_max_rate | 214.000s | 13043.743us | 1 | 1 | 100.00 | |
| health_checks | 0 | 1 | 0.00 | |||
| entropy_src_rng | 136.000s | 6275.917us | 0 | 1 | 0.00 | |
| conditioning | 0 | 1 | 0.00 | |||
| entropy_src_rng | 136.000s | 6275.917us | 0 | 1 | 0.00 | |
| interrupts | 1 | 2 | 50.00 | |||
| entropy_src_rng | 136.000s | 6275.917us | 0 | 1 | 0.00 | |
| entropy_src_intr | 12.000s | 4522.525us | 1 | 1 | 100.00 | |
| alerts | 1 | 2 | 50.00 | |||
| entropy_src_rng | 136.000s | 6275.917us | 0 | 1 | 0.00 | |
| entropy_src_functional_alerts | 5.000s | 878.266us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| entropy_src_stress_all | 200.000s | 14398.492us | 1 | 1 | 100.00 | |
| functional_errors | 1 | 1 | 100.00 | |||
| entropy_src_functional_errors | 3.000s | 111.048us | 1 | 1 | 100.00 | |
| firmware_ov_read_contiguous_data | 1 | 1 | 100.00 | |||
| entropy_src_fw_ov_contiguous | 3.000s | 34.163us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| entropy_src_intr_test | 1.000s | 69.667us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| entropy_src_alert_test | 7.000s | 56.010us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| entropy_src_tl_errors | 2.000s | 32.830us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| entropy_src_tl_errors | 2.000s | 32.830us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| entropy_src_csr_hw_reset | 3.000s | 140.628us | 1 | 1 | 100.00 | |
| entropy_src_csr_rw | 2.000s | 27.127us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 3.000s | 141.379us | 1 | 1 | 100.00 | |
| entropy_src_same_csr_outstanding | 3.000s | 164.379us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| entropy_src_csr_hw_reset | 3.000s | 140.628us | 1 | 1 | 100.00 | |
| entropy_src_csr_rw | 2.000s | 27.127us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 3.000s | 141.379us | 1 | 1 | 100.00 | |
| entropy_src_same_csr_outstanding | 3.000s | 164.379us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| entropy_src_sec_cm | 2.000s | 84.983us | 1 | 1 | 100.00 | |
| entropy_src_tl_intg_err | 4.000s | 364.363us | 1 | 1 | 100.00 | |
| sec_cm_config_regwen | 1 | 2 | 50.00 | |||
| entropy_src_rng | 136.000s | 6275.917us | 0 | 1 | 0.00 | |
| entropy_src_cfg_regwen | 2.000s | 94.944us | 1 | 1 | 100.00 | |
| sec_cm_config_mubi | 0 | 1 | 0.00 | |||
| entropy_src_rng | 136.000s | 6275.917us | 0 | 1 | 0.00 | |
| sec_cm_config_redun | 0 | 1 | 0.00 | |||
| entropy_src_rng | 136.000s | 6275.917us | 0 | 1 | 0.00 | |
| sec_cm_intersig_mubi | 0 | 2 | 0.00 | |||
| entropy_src_rng | 136.000s | 6275.917us | 0 | 1 | 0.00 | |
| entropy_src_fw_ov | 70.000s | 5309.942us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_fsm_sparse | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 3.000s | 111.048us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 2.000s | 84.983us | 1 | 1 | 100.00 | |
| sec_cm_ack_sm_fsm_sparse | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 3.000s | 111.048us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 2.000s | 84.983us | 1 | 1 | 100.00 | |
| sec_cm_rng_bkgn_chk | 0 | 1 | 0.00 | |||
| entropy_src_rng | 136.000s | 6275.917us | 0 | 1 | 0.00 | |
| sec_cm_fifo_ctr_redun | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 3.000s | 111.048us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 2.000s | 84.983us | 1 | 1 | 100.00 | |
| sec_cm_ctr_redun | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 3.000s | 111.048us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 2.000s | 84.983us | 1 | 1 | 100.00 | |
| sec_cm_ctr_local_esc | 1 | 1 | 100.00 | |||
| entropy_src_functional_errors | 3.000s | 111.048us | 1 | 1 | 100.00 | |
| sec_cm_esfinal_rdata_bus_consistency | 1 | 1 | 100.00 | |||
| entropy_src_functional_alerts | 5.000s | 878.266us | 1 | 1 | 100.00 | |
| sec_cm_tile_link_bus_integrity | 1 | 1 | 100.00 | |||
| entropy_src_tl_intg_err | 4.000s | 364.363us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| external_health_tests | 1 | 1 | 100.00 | |||
| entropy_src_rng_with_xht_rsps | 308.000s | 14028.903us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| entropy_src_stress_all_with_rand_reset | 25.000s | 963.658us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (entropy_src_scoreboard.sv:2130) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: entropy_src_reg_block.ht_watermark | 1 test run | |||
| entropy_src_rng | 83813563145701520177825704503558727733548868131406258769923243610427914511178 | 1935 |
UVM_INFO @ 6275916519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_WARNING (uvm_reg_field.svh:1186) [RegModel] Trying to predict value of field 'observe_fifo_depth' while register 'entropy_src_reg_block.observe_fifo_depth' is being accessed | 1 test run | |||
| entropy_src_stress_all_with_rand_reset | 71166842604886247575343153299873536904765430184812702305814946064772170380527 | 1345 |
UVM_FATAL @ 963658316 ps: (entropy_src_scoreboard.sv:1601) [uvm_test_top.env.scoreboard] Check failed (ral.observe_fifo_depth.observe_fifo_depth.predict( ral.observe_fifo_depth.observe_fifo_depth.get_mirrored_value()-1, .kind(UVM_PREDICT_DIRECT)))
UVM_INFO @ 963658316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_alert triggered unexpectedly | 1 test run | |||
| entropy_src_fw_ov | 44007541266892010567155499836942317044562429677724728152850615601329574979489 | 640 |
UVM_INFO @ 5309942374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_hi_total_fails | 1 test run | |||
| entropy_src_csr_mem_rw_with_rand_reset | 13672986651001451622644022784060028850753377377125236951324265703976046683021 | 113 |
UVM_INFO @ 30814857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|