Simulation Results

Simulation Results: i2c

22/07/2026 19:39:31 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.16 %

code
85.56 %

assert
96.19 %

func
79.74 %

block
95.93 %

line
95.34 %

branch
92.69 %

toggle
72.19 %

FSM
82.01 %

Validation stages

V1		100.00%
V2		85.37%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	195.000s	3224.141us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	7.000s	616.434us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	2.000s	49.438us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	91.818us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.000s	98.626us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	434.790us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	2.000s	29.767us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	91.818us	1	1	100.00
	i2c_csr_aliasing	2.000s	434.790us	1	1	100.00

35/41 passed

85.37 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.000s	113.172us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	104.000s	46825.925us	0	1	0.00
host_maxperf				0	1	0.00
	i2c_host_perf	3600.000s	0.000us	0	1	0.00
host_override				1	1	100.00
	i2c_host_override	2.000s	55.712us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	1877.000s	5962.567us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	1792.000s	8782.793us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	94.260us	1	1	100.00
	i2c_host_fifo_fmt_empty	93.000s	534.121us	1	1	100.00
	i2c_host_fifo_reset_rx	4.000s	191.347us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	1253.000s	2797.652us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	15.000s	466.177us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	6.000s	438.903us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	4.000s	519.788us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	156.000s	26659.501us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	5.000s	491.858us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	39.000s	5282.044us	1	1	100.00
	i2c_target_intr_smoke	3.000s	2267.184us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	275.658us	1	1	100.00
	i2c_target_fifo_reset_tx	3.000s	699.177us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	7.000s	8098.898us	1	1	100.00
	i2c_target_stress_rd	39.000s	5282.044us	1	1	100.00
	i2c_target_intr_stress_wr	12.000s	4227.569us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	8.000s	5642.928us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	2.000s	214.378us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	10.000s	1272.111us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	4.000s	689.490us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	5.000s	1845.998us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	479.323us	1	1	100.00
host_mode_config_perf				0	2	0.00
	i2c_host_perf	3600.000s	0.000us	0	1	0.00
	i2c_host_perf_precise	3600.000s	0.000us	0	1	0.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	15.000s	466.177us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.000s	258.935us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	4.000s	800.097us	1	1	100.00
	i2c_target_nack_acqfull_addr	5.000s	441.425us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	263.558us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	14.000s	703.186us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	3.000s	416.213us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	2.000s	25.056us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	19.341us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.000s	197.941us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.000s	197.941us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	49.438us	1	1	100.00
	i2c_csr_rw	1.000s	91.818us	1	1	100.00
	i2c_csr_aliasing	2.000s	434.790us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	40.256us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	49.438us	1	1	100.00
	i2c_csr_rw	1.000s	91.818us	1	1	100.00
	i2c_csr_aliasing	2.000s	434.790us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	40.256us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.000s	49.841us	1	1	100.00
	i2c_sec_cm	2.000s	68.169us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.000s	49.841us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	11.000s	11980.593us	1
target_error_intr				1
	i2c_target_unexp_stop	3.000s	1040.107us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	20.000s	1014.331us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				3 test runs
	i2c_host_error_intr	113677026529802067562761311518360125948200702612342604964493127928827469572368	105	UVM_INFO @ 113172074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	76668583613762274014873409538719032188644297215107831396266994600760733021381	135	UVM_INFO @ 46825924998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	2022886903745735681913043303470379967102674425387071744073047664586374012040	109	UVM_INFO @ 1014330832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				2 test runs
	i2c_host_perf	45191738199242027416801826826558779721589296298229499137153124699857601376524	None
	i2c_host_perf_precise	105377730928631674009076802036042746675919627901795813364066922873560599693529	None
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	92713756459453567869206848476921956529177932259103420317222378122433478671788	93	UVM_INFO @ 519788343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/i2c-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_i2c_/rtl/i2c_fifos.sv,320): Assertion TxWriteStableBeforeHandshake_A has failed (* cycles, starting * PS)				1 test run
	i2c_target_unexp_stop	14666212703902416286937855351027035420501819305972306583226774573754034946738	89	UVM_ERROR @ 1040106579 ps: (i2c_fifos.sv:320) [ASSERT FAILED] TxWriteStableBeforeHandshake_A UVM_INFO @ 1040106579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	113896558949477566664042765924574809371551234693074743473442858410916437290569	98	UVM_INFO @ 11980593166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:				1 test run
	i2c_host_mode_toggle	90421606266087976153801956422687423859102106076907354055506566980526887923160	94	---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @17162