Simulation Results: lc_ctrl/volatile_unlock_disabled

 
22/07/2026 19:39:31 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.96 %
  • code
  • 92.58 %
  • assert
  • 96.69 %
  • func
  • 86.62 %
  • block
  • 96.66 %
  • line
  • 97.35 %
  • branch
  • 91.49 %
  • toggle
  • 86.25 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 35.504us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 87.895us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 147.770us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 196.231us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 161.947us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 30.544us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 147.770us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 161.947us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 249.522us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 277.880us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 14.324us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 34.505us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 5.000s 971.911us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.000s 459.068us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 5.000s 971.911us 1 1 100.00
lc_ctrl_prog_failure 3.000s 34.505us 1 1 100.00
lc_ctrl_errors 8.000s 459.068us 1 1 100.00
lc_ctrl_security_escalation 7.000s 1513.186us 1 1 100.00
lc_ctrl_jtag_state_failure 12.000s 4305.189us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 415.815us 1 1 100.00
lc_ctrl_jtag_errors 24.000s 25663.859us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 7.000s 310.695us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.000s 2193.690us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 415.815us 1 1 100.00
lc_ctrl_jtag_errors 24.000s 25663.859us 1 1 100.00
lc_ctrl_jtag_access 2.000s 230.901us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 23.000s 1515.467us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 96.577us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 248.280us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.000s 1211.526us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.000s 4088.825us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 44.823us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 813.360us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 160.163us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.000s 865.746us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 15.057us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 20.000s 12654.973us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 20.182us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 26.197us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 26.197us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 87.895us 1 1 100.00
lc_ctrl_csr_rw 2.000s 147.770us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 161.947us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 172.666us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 87.895us 1 1 100.00
lc_ctrl_csr_rw 2.000s 147.770us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 161.947us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 172.666us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 465.533us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 174.587us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 174.587us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 277.880us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 971.911us 1 1 100.00
lc_ctrl_sec_cm 3.000s 465.533us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 971.911us 1 1 100.00
lc_ctrl_sec_cm 3.000s 465.533us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 971.911us 1 1 100.00
lc_ctrl_sec_cm 3.000s 465.533us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 971.911us 1 1 100.00
lc_ctrl_sec_cm 3.000s 465.533us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 971.911us 1 1 100.00
lc_ctrl_sec_cm 3.000s 465.533us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 971.911us 1 1 100.00
lc_ctrl_sec_cm 3.000s 465.533us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 971.911us 1 1 100.00
lc_ctrl_sec_cm 3.000s 465.533us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 5.000s 971.911us 1 1 100.00
lc_ctrl_sec_cm 3.000s 465.533us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.000s 1513.186us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 249.522us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.000s 2193.690us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 13.000s 944.857us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 13.000s 944.857us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.000s 2440.753us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 241.927us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 241.927us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 13.000s 2053.820us 1 1 100.00