Simulation Results: lc_ctrl/volatile_unlock_enabled

 
22/07/2026 19:39:31 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.02 %
  • code
  • 93.55 %
  • assert
  • 96.54 %
  • func
  • 85.99 %
  • block
  • 97.07 %
  • line
  • 97.63 %
  • branch
  • 92.56 %
  • toggle
  • 86.37 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.000s 149.200us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 54.674us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 16.358us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 45.098us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 84.047us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 46.079us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 16.358us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 84.047us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 77.889us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 273.868us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 13.472us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 158.040us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 235.846us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.000s 617.611us 1 1 100.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 4.000s 235.846us 1 1 100.00
lc_ctrl_prog_failure 3.000s 158.040us 1 1 100.00
lc_ctrl_errors 7.000s 617.611us 1 1 100.00
lc_ctrl_security_escalation 7.000s 629.248us 1 1 100.00
lc_ctrl_jtag_state_failure 2.000s 116.867us 0 1 0.00
lc_ctrl_jtag_prog_failure 5.000s 279.036us 1 1 100.00
lc_ctrl_jtag_errors 11.000s 946.300us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 6.000s 2143.216us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.000s 2448.869us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.000s 279.036us 1 1 100.00
lc_ctrl_jtag_errors 11.000s 946.300us 1 1 100.00
lc_ctrl_jtag_access 18.000s 8149.354us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.000s 6145.326us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 4.000s 400.758us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 72.306us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 14.000s 2104.476us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.000s 205.998us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 17.483us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 560.409us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 98.538us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 42.000s 2832.441us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 22.245us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 12.000s 3100.013us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 43.320us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 151.366us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 151.366us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 54.674us 1 1 100.00
lc_ctrl_csr_rw 2.000s 16.358us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 84.047us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 18.009us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 54.674us 1 1 100.00
lc_ctrl_csr_rw 2.000s 16.358us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 84.047us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 18.009us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 494.351us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 157.563us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 157.563us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 273.868us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 235.846us 1 1 100.00
lc_ctrl_sec_cm 3.000s 494.351us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 235.846us 1 1 100.00
lc_ctrl_sec_cm 3.000s 494.351us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 235.846us 1 1 100.00
lc_ctrl_sec_cm 3.000s 494.351us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 235.846us 1 1 100.00
lc_ctrl_sec_cm 3.000s 494.351us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 235.846us 1 1 100.00
lc_ctrl_sec_cm 3.000s 494.351us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 235.846us 1 1 100.00
lc_ctrl_sec_cm 3.000s 494.351us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 235.846us 1 1 100.00
lc_ctrl_sec_cm 3.000s 494.351us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 235.846us 1 1 100.00
lc_ctrl_sec_cm 3.000s 494.351us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.000s 629.248us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 77.889us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.000s 2448.869us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 1642.235us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 1642.235us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 2821.186us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 1132.941us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 1132.941us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 2.000s 103.403us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_jtag_state_failure 26586353422155446322294519440049977676063202928637880393274666971701095284519 179
UVM_INFO @ 116867435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 62130726800647712291051553309339403403164871682955463362500757838738868149112 161
UVM_INFO @ 103402544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---