Simulation Results: mbx

 
22/07/2026 19:39:31 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.32 %
  • code
  • 91.52 %
  • assert
  • 97.62 %
  • func
  • 84.82 %
  • block
  • 96.88 %
  • line
  • 96.71 %
  • branch
  • 91.89 %
  • toggle
  • 85.96 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 38.000s 26060.025us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 33.111us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 2.000s 53.198us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 3.000s 100.710us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 1.000s 30.964us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
mbx_csr_mem_rw_with_rand_reset 1.000s 76.104us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 2.000s 53.198us 1 1 100.00
mbx_csr_aliasing 1.000s 30.964us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 1 100.00
mbx_stress 81.000s 5119.321us 1 1 100.00
mbx_max_activity 1 1 100.00
mbx_stress_zero_delays 68.000s 6716.815us 1 1 100.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 49.000s 36330.182us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 9.000s 3008.009us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 25.503us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 15.783us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 24.218us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 24.218us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 33.111us 1 1 100.00
mbx_csr_rw 2.000s 53.198us 1 1 100.00
mbx_csr_aliasing 1.000s 30.964us 1 1 100.00
mbx_same_csr_outstanding 2.000s 69.643us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 33.111us 1 1 100.00
mbx_csr_rw 2.000s 53.198us 1 1 100.00
mbx_csr_aliasing 1.000s 30.964us 1 1 100.00
mbx_same_csr_outstanding 2.000s 69.643us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 652.344us 1 1 100.00
mbx_sec_cm 1.000s 13.762us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 1 test run
mbx_tl_errors 7770736190098923914011565703489665671384141830934094757495060095017223622736 85
TL item was: req: (cip_tl_seq_item@18021) { a_addr: 'h897dcb0 a_data: 'h596cdcad a_mask: 'h1 a_size: 'h1 a_param: 'h0 a_source: 'hc a_opcode: 'h1 a_user: 'h246aa d_param: 'h0 d_source: 'hc d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 24218462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---