Simulation Results: otbn

 
22/07/2026 19:39:31 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.04 %
  • code
  • 86.16 %
  • assert
  • 90.35 %
  • func
  • 96.61 %
  • block
  • 99.27 %
  • line
  • 99.47 %
  • branch
  • 94.73 %
  • toggle
  • 84.24 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 11.000s 78.219us 1 1 100.00
single_binary 1 1 100.00
otbn_single 7.000s 15.715us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 6.000s 22.120us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 5.000s 15.254us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 6.000s 176.951us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 3.000s 25.304us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 9.000s 67.691us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 5.000s 15.254us 1 1 100.00
otbn_csr_aliasing 3.000s 25.304us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 93.000s 24205.360us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 27.000s 2550.318us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 21.000s 887.472us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 83.000s 831.447us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 103.000s 1389.917us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 70.000s 273.096us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 9.000s 58.075us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 5.000s 17.355us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 7.000s 118.983us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 5.000s 48.853us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 21.860us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 11.000s 554.637us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 11.000s 554.637us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 6.000s 22.120us 1 1 100.00
otbn_csr_rw 5.000s 15.254us 1 1 100.00
otbn_csr_aliasing 3.000s 25.304us 1 1 100.00
otbn_same_csr_outstanding 4.000s 47.353us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 6.000s 22.120us 1 1 100.00
otbn_csr_rw 5.000s 15.254us 1 1 100.00
otbn_csr_aliasing 3.000s 25.304us 1 1 100.00
otbn_same_csr_outstanding 4.000s 47.353us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 8.000s 30.616us 1 1 100.00
otbn_dmem_err 7.000s 13.491us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 21.000s 123.636us 1 1 100.00
otbn_controller_ispr_rdata_err 8.000s 217.075us 1 1 100.00
otbn_mac_bignum_acc_err 11.000s 307.262us 1 1 100.00
otbn_urnd_err 5.000s 77.283us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 5.000s 85.426us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 6.000s 92.801us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 31.120us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 287.000s 1588.556us 1 1 100.00
otbn_tl_intg_err 30.000s 182.477us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 43.000s 794.125us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 287.000s 1588.556us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 287.000s 1588.556us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 11.000s 78.219us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 7.000s 13.491us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 8.000s 30.616us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 30.000s 182.477us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 58.075us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 30.616us 1 1 100.00
otbn_dmem_err 7.000s 13.491us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 17.355us 1 1 100.00
otbn_illegal_mem_acc 5.000s 85.426us 1 1 100.00
otbn_sec_cm 287.000s 1588.556us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 287.000s 1588.556us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 7.000s 15.715us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 30.616us 1 1 100.00
otbn_dmem_err 7.000s 13.491us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 17.355us 1 1 100.00
otbn_illegal_mem_acc 5.000s 85.426us 1 1 100.00
otbn_sec_cm 287.000s 1588.556us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 287.000s 1588.556us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 58.075us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 8.000s 30.616us 1 1 100.00
otbn_dmem_err 7.000s 13.491us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 17.355us 1 1 100.00
otbn_illegal_mem_acc 5.000s 85.426us 1 1 100.00
otbn_sec_cm 287.000s 1588.556us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 287.000s 1588.556us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 7.000s 15.715us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 6.000s 37.958us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 36.785us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 27.000s 949.129us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 27.000s 949.129us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 9.000s 64.018us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 287.000s 1588.556us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 287.000s 1588.556us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 0 1 0.00
otbn_rf_bignum_intg_err 7.000s 434.241us 0 1 0.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 287.000s 1588.556us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 287.000s 1588.556us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 9.000s 43.824us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 9.000s 43.824us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 12.000s 41.154us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 7.000s 15.715us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 7.000s 15.715us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 7.000s 15.715us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 103.000s 1389.917us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 7.000s 15.715us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 7.000s 15.715us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 9.000s 27.839us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 7.000s 15.715us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 287.000s 1588.556us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 31.000s 460.369us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 72.421us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
otbn_rf_bignum_intg_err 42516201318815397685399312462662562462062944344976070659437222644633335982082 107
UVM_INFO @ 434240858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 27023360704648873903725266857487093862462295978832357190216733005116274981396 156
UVM_INFO @ 460369371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---