Simulation Results: otp_ctrl

 
22/07/2026 19:39:31 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 74.06 %
  • code
  • 71.99 %
  • assert
  • 94.13 %
  • func
  • 56.06 %
  • line
  • 87.40 %
  • branch
  • 83.99 %
  • cond
  • 85.63 %
  • toggle
  • 67.20 %
  • FSM
  • 35.72 %
Validation stages
V1
100.00%
V2
70.00%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.740s 82.035us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 9.190s 2878.153us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.040s 323.209us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.660s 187.886us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 3.540s 113.990us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 9.920s 1525.987us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.920s 121.856us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.660s 187.886us 1 1 100.00
otp_ctrl_csr_aliasing 9.920s 1525.987us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.580s 70.449us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.220s 137.490us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 97.710s 2903.132us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.040s 278.884us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 21.800s 3433.727us 0 1 0.00
otp_ctrl_check_fail 1.860s 99.588us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 9.510s 2664.934us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 4.910s 1273.799us 0 1 0.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 24.500s 1624.180us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 9.140s 887.758us 1 1 100.00
otp_ctrl_parallel_lc_esc 6.820s 167.776us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 24.790s 1440.400us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 6.170s 343.235us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 12.600s 7277.598us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 27.300s 7203.387us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.480s 84.705us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.140s 781.068us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.490s 227.673us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.490s 227.673us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.040s 323.209us 1 1 100.00
otp_ctrl_csr_rw 1.660s 187.886us 1 1 100.00
otp_ctrl_csr_aliasing 9.920s 1525.987us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.710s 150.690us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.040s 323.209us 1 1 100.00
otp_ctrl_csr_rw 1.660s 187.886us 1 1 100.00
otp_ctrl_csr_aliasing 9.920s 1525.987us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.710s 150.690us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 262.280s 31333.946us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 262.280s 31333.946us 1 1 100.00
otp_ctrl_tl_intg_err 11.850s 745.689us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 262.280s 31333.946us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 262.280s 31333.946us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 11.850s 745.689us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 9.190s 2878.153us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 9.190s 2878.153us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 262.280s 31333.946us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 262.280s 31333.946us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 262.280s 31333.946us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 262.280s 31333.946us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 262.280s 31333.946us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 262.280s 31333.946us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 262.280s 31333.946us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 262.280s 31333.946us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 262.280s 31333.946us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 262.280s 31333.946us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 262.280s 31333.946us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 262.280s 31333.946us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 262.280s 31333.946us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 262.280s 31333.946us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 262.280s 31333.946us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.820s 167.776us 1 1 100.00
otp_ctrl_sec_cm 262.280s 31333.946us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.820s 167.776us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.820s 167.776us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.820s 167.776us 1 1 100.00
otp_ctrl_macro_errs 6.170s 343.235us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.820s 167.776us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.820s 167.776us 1 1 100.00
otp_ctrl_sec_cm 262.280s 31333.946us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.820s 167.776us 1 1 100.00
otp_ctrl_sec_cm 262.280s 31333.946us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.820s 167.776us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.820s 167.776us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.820s 167.776us 1 1 100.00
otp_ctrl_macro_errs 6.170s 343.235us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.820s 167.776us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.820s 167.776us 1 1 100.00
otp_ctrl_sec_cm 262.280s 31333.946us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.040s 278.884us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 1.860s 99.588us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 4.910s 1273.799us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 4.910s 1273.799us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 4.910s 1273.799us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 4.910s 1273.799us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 4.910s 1273.799us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 9.190s 2878.153us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 4.910s 1273.799us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 9.190s 2878.153us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 262.280s 31333.946us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 9.510s 2664.934us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 9.190s 2878.153us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 9.190s 2878.153us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 6.170s 343.235us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 97.570s 62979.594us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 35.490s 3005.696us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 3 test runs
otp_ctrl_background_chks 102980798154838053795523143403286755832711251811433409336747560234483835667165 26976
UVM_INFO @ 3433727336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 45265672564646736418042088753745566289894490954788782723906171910415359854658 10102
UVM_INFO @ 3005696254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 113417908459060826848257821429946664369272776147826412305758003246133622065017 16171
UVM_INFO @ 7203386678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 2 test runs
otp_ctrl_dai_lock 59046692330903777727593001153508109015696091089679132083175333715705985318222 3461
UVM_INFO @ 1273798895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 56485950261704297905215452970741356975025618218508114394573353788827920142250 160
UVM_INFO @ 99587637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 1 test run
otp_ctrl_partition_walk 20827919433748484001172501231456057604867933575389815230666045949564622851043 160055
UVM_INFO @ 2903131786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 106387220267435637446232662150968433928931060580406741018527399726457383434865 89
UVM_INFO @ 62979593545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 85451649618241587478377769550769918858806359334976014389238826772151179060022 3506
UVM_INFO @ 343234585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---