Simulation Results: rom_ctrl/32kb

 
22/07/2026 19:39:31 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.48 %
  • code
  • 93.25 %
  • assert
  • 97.67 %
  • func
  • 83.53 %
  • block
  • 95.24 %
  • line
  • 95.48 %
  • branch
  • 93.28 %
  • toggle
  • 84.22 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.000s 1170.658us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.000s 170.053us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.000s 171.921us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.000s 297.996us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 130.680us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.000s 484.429us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.000s 171.921us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 130.680us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.000s 130.952us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.000s 401.835us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 4.000s 229.895us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 10.000s 2345.174us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.000s 1703.998us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 5.000s 1677.783us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 387.420us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 387.420us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.000s 170.053us 1 1 100.00
rom_ctrl_csr_rw 4.000s 171.921us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 130.680us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 520.715us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.000s 170.053us 1 1 100.00
rom_ctrl_csr_rw 4.000s 171.921us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 130.680us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 520.715us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 28.000s 1436.373us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 10.000s 403.649us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 100.000s 5452.434us 1 1 100.00
rom_ctrl_tl_intg_err 14.000s 3449.495us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 100.000s 5452.434us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 100.000s 5452.434us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 28.000s 1436.373us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 28.000s 1436.373us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 28.000s 1436.373us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 28.000s 1436.373us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 28.000s 1436.373us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 100.000s 5452.434us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 100.000s 5452.434us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.000s 1170.658us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.000s 1170.658us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.000s 1170.658us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 14.000s 3449.495us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 28.000s 1436.373us 1 1 100.00
rom_ctrl_kmac_err_chk 6.000s 1703.998us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 28.000s 1436.373us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 28.000s 1436.373us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 28.000s 1436.373us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 10.000s 403.649us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 100.000s 5452.434us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 43.000s 2622.522us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 93233650752979125379295599057506018443564777562440941743159117887009935152321 88
UVM_INFO @ 229894704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---