Simulation Results: rstmgr

 
22/07/2026 19:39:31 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.40 %
  • code
  • 99.16 %
  • assert
  • 98.17 %
  • func
  • 94.88 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.41 %
  • toggle
  • 99.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.300s 58.437us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.590s 93.275us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.800s 35.605us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.510s 122.439us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.440s 40.005us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.440s 68.543us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.800s 35.605us 1 1 100.00
rstmgr_csr_aliasing 1.440s 40.005us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.850s 53.558us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.030s 39.404us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.750s 40.888us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.620s 796.808us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.620s 796.808us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.620s 796.808us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.620s 796.808us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 20.240s 3315.170us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.040s 41.618us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.910s 48.705us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.910s 48.705us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.590s 93.275us 1 1 100.00
rstmgr_csr_rw 0.800s 35.605us 1 1 100.00
rstmgr_csr_aliasing 1.440s 40.005us 1 1 100.00
rstmgr_same_csr_outstanding 1.170s 37.188us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.590s 93.275us 1 1 100.00
rstmgr_csr_rw 0.800s 35.605us 1 1 100.00
rstmgr_csr_aliasing 1.440s 40.005us 1 1 100.00
rstmgr_same_csr_outstanding 1.170s 37.188us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 39.090s 7961.067us 1 1 100.00
rstmgr_tl_intg_err 2.510s 333.026us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 39.090s 7961.067us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 39.090s 7961.067us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.510s 333.026us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.030s 58.227us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.110s 424.766us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.020s 292.274us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 39.090s 7961.067us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.800s 35.605us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.800s 35.605us 1 1 100.00