Simulation Results

Simulation Results: rv_dm/use_dmi_interface

22/07/2026 19:39:31 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.73 %

code
74.47 %

assert
96.90 %

func
91.80 %

block
90.02 %

line
89.93 %

branch
72.94 %

toggle
72.53 %

FSM
62.50 %

Validation stages

V1		96.30%
V2		69.57%
V2S		100.00%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	32.000s	2178.497us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	30.000s	682.255us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	31.000s	120.262us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	57.000s	26818.415us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	32.000s	590.489us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	35.000s	10715.854us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	33.000s	2908.283us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	46.000s	51137.775us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	54.000s	40693.475us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	32.000s	751.223us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	31.000s	275.204us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	31.000s	146.495us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	31.000s	107.066us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	31.000s	160.969us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	32.000s	325.464us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	31.000s	420.593us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	33.000s	1572.651us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	32.000s	751.223us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	30.000s	215.486us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	31.000s	692.773us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	31.000s	146.495us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	30.000s	68.419us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	38.000s	244.178us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	33.000s	378.417us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	47.000s	1124.832us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	44.000s	2300.559us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	36.000s	232.713us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	44.000s	2300.559us	1	1	100.00
	rv_dm_csr_rw	33.000s	378.417us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	31.000s	55.353us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	30.000s	124.982us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	32.000s	2178.497us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	31.000s	519.700us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	31.000s	335.508us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	31.000s	165.834us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	32.000s	732.244us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	36.000s	1337.132us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	30.000s	383.128us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	32.000s	58.851us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	36.000s	3517.412us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	33.000s	172.275us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	34.000s	5726.910us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	32.000s	117.883us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	32.000s	322.082us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	40.000s	7293.891us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	42.000s	7455.630us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	32.000s	271.274us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	31.000s	2344.881us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	30.000s	81.154us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	33.000s	593.957us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	33.000s	593.957us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	44.000s	2300.559us	1	1	100.00
	rv_dm_csr_hw_reset	38.000s	244.178us	1	1	100.00
	rv_dm_csr_rw	33.000s	378.417us	1	1	100.00
	rv_dm_same_csr_outstanding	35.000s	957.999us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	44.000s	2300.559us	1	1	100.00
	rv_dm_csr_hw_reset	38.000s	244.178us	1	1	100.00
	rv_dm_csr_rw	33.000s	378.417us	1	1	100.00
	rv_dm_same_csr_outstanding	35.000s	957.999us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	31.000s	2346.933us	1	1	100.00
	rv_dm_tl_intg_err	42.000s	7202.896us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	42.000s	7202.896us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	34.000s	5726.910us	1	1	100.00
	rv_dm_debug_disabled	31.000s	115.794us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	34.000s	5726.910us	1	1	100.00
	rv_dm_debug_disabled	31.000s	115.794us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	32.000s	2178.497us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	31.000s	434.477us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	30.000s	116.801us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	30.000s	116.801us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	31.000s	434.477us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	37.000s	1554.821us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	426.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				2 test runs
	rv_dm_sba_tl_access	44024151087452717353049218131598425636972651496653349359715931938236011750249	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23863
	rv_dm_autoincr_sba_tl_access	84167461715505157565778231915506175229704469559953466901604565507726871004631	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10071
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				2 test runs
	rv_dm_delayed_resp_sba_tl_access	97607648424275634079550587189434102497423019801839608427406960398893232860947	107	UVM_INFO @ 383127886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	113216054425712000261371514889380587461426384803084968851947965332938528137254	107	UVM_INFO @ 58851069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				2 test runs
	rv_dm_hart_unavail	62855667933785308239551639255313611080205716148442212035657064850637753041752	87	UVM_INFO @ 322082405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	65439450841628227656342396926457475242679244727406293314117258862590244046830	95	UVM_INFO @ 1554821154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				2 test runs
	rv_dm_jtag_dmi_debug_disabled	11299806305339459403231492004560944093838568950290960152273706848349184859807	87	UVM_INFO @ 172274562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	80720637113836804578797099043339706375054731380609570149552416057428179361519	91	UVM_INFO @ 2344881461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				1 test run
	rv_dm_mem_tl_access_resuming	571857439630307671926230776343652008667743113533470927312414912077583583149	87	UVM_INFO @ 107065835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	58267471818099139173478871868520000242453367019273403382074356607284407132832	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---